Tft array substrate, liquid crystal display device, manufacturing methods of tft array substrate and liquid crystal display device, and electronic device

ABSTRACT

A TFT array substrate includes a thin film transistor section in which a gate electrode is formed on a substrate, and a semiconductor layer is formed on the gate electrode via a gate insulation layer. The semiconductor layer of this TFT array substrate has a shape formed by dropping a droplet. Accordingly, it is possible to directly forming a semiconductor layer, or a resist layer for forming the semiconductor layer, by dropping a droplet(s). On this account, the present invention allows the use of an inkjet method, thus reducing costs and numbers of manufacturing processes.

TECHNICAL FIELD

The present invention relates to a TFT array substrate; a liquid crystaldisplay device; manufacturing methods of the TFT array substrate and theliquid crystal display device; and an electronic device.

BACKGROUND ART

Conventionally, for a liquid crystal display device including a TFT(Thin Film Transistor), a TFT array substrate is manufactured through aseries of manufacturing steps, as shown in FIG. 28. More specifically,the manufacturing method of a conventional TFT array substrate iscarried out through the steps of depositing a material for gate line,forming the gate line, depositing a gate insulation layer and depositinga semiconductor layer, forming the semiconductor layer, depositing amaterial for source line and drain line, forming the source line and thedrain line, processing a channel section, which exists between thesource and the drain electrode on the semiconductor layer, forming apassivation film, processing the passivation film, depositing a pixelelectrode, and forming the pixel electrode (101 through 111).

Among these steps, the gate line forming step 102, the semiconductorlayer forming step 104, the source/drain lines forming step 106, thepassivation film processing step 109, and the pixel electrode formingstep 111, which involves photolithography and etching performed with amask. More specifically, these steps use photolithography and etching soas to process the film formed through the previous steps, i.e., the gateline depositing step 101, the gate insulation layer/semiconductor layerdepositing step 103, the source/drain lines depositing step 105, thepassivation film forming step 108, and the pixel electrode depositingstep 110.

Meanwhile, there has been a technique proposed in recent years, whichforms wiring by an inkjet method without using photolithography. In thistechnique, the substrate is provided with two areas respectively havingan affinity characteristic and a non-affinity characteristic withrespect to a liquid material of the wiring, in a surface to which thewiring will be formed; and the liquid of the wiring material is droppedby an inkjet method onto the affinity area so as to form the wiring.Hereinafter, the areas having an affinity characteristic and anon-affinity characteristic with respect to a general liquid including aliquid wiring material are referred to as a lyophilic area and alyophobic area, respectively; and the areas having an affinitycharacteristic and a non-affinity characteristic with respect to anaqueous liquid are referred to as a hydrophilic area and a hydrophobicarea, respectively. Such a technique is disclosed in a Document 1(Japanese Laid-Open Patent Application Tokukaihei 11-204529/1999(published on Jul. 30, 1999)).

Further, another wiring forming technique using an inkjet method isdisclosed in a Document 2 (Japanese Laid-Open Patent Application Tokukai2000-353594/2000 (published on Dec. 19, 2000)). In this method, thewiring forming area is provided with banks on the respective ends so asto keep the wiring material within the area. In this technique, theupper portion of the bank is lyophobic, and the wiring forming area islyophilic.

Further, still another wiring forming technique using an inkjet methodis disclosed in a Document 3 (SID 01 DIGEST 2001, Page 40 to 43, 6.1:Invited Paper: All-Polymer Thin Film Transistors Fabricated byHigh-Resolution Inkjet Printing (by Takeo Kawase and other writers) inwhich a TFT is formed only by organic materials.

As described, the conventional manufacturing method of a TFT arraysubstrate involving photolithography uses masks at least in thefollowing five steps: the gate line forming step 102, the semiconductorlayer forming step 104, the source/drain lines forming step 106, thepassivation film processing step 109, and the pixel electrode formingstep 111.

Further, the conventional method uses vacuum equipments in therespective deposition steps, and also in the respective processing steps(forming and processing steps) after the deposition. Accordingly, inorder to meet the recent market demand for a larger liquid crystaldisplay device, the conventional method consumes enormous cost, as theTFTs are formed by such a manner with respect to a large-sizedsubstrate.

Furthermore, the demand for a larger substrate brings about greaterconsumption of resists or wiring material. Meanwhile, the materials(such as a resist) used in the processing steps for forming the wiringetc., are removed and discarded by etching or removing, since aneffective reusing method of those has not yet been realized.Accordingly, works and costs for the discard are growing bigger with thedemand for a larger substrate, as well as environmental burden due tothe discarded material. As described, the conventional manufacturingmethod of a TFT array substrate, which mainly involves photolithography,requires more manufacturing steps and a greater cost.

On the other hand, as disclosed in the foregoing Documents, themanufacturing method of a TFT array substrate using an inkjet methodrequires less number of masks. Therefore, there has been a demand fordevelopment of the inkjet method as a technique for realizing reductionin both manufacturing steps and costs.

DISCLOSURE OF INVENTION

A TFT array substrate according to the present invention includes: athin film transistor section in which a gate electrode is formed on asubstrate, and a semiconductor layer is formed on the gate electrode viaa gate insulation layer, the semiconductor layer having a shape formedby dropping a droplet.

With this arrangement, since the semiconductor layer has a shape of adropped droplet(s) (substantially a circular shape, or a shape made ofplural overlapped circles, for example), the semiconductor layer can beformed by dropping a droplet(s) of a semiconductor material by using aninkjet method. Alternatively, the semiconductor layer may be formed insuch a manner that a resist layer is formed by dropping a droplet(s) ofa resist material onto a semiconductor film by an inkjet method, and theresist layer is used as a mask for processing a semiconductor film.Further, the resist material may instead be a conductive material, and aconductor forming layer may be formed by dropping the droplet(s) of theconductive material by an inkjet method so as to be used as a mask forforming the semiconductor layer.

With this method, it is possible to manufacture the TFT array substratewithout a mask for forming a semiconductor layer. Accordingly, therequired number of masks in the manufacturing is reduced, thus reducingmanufacturing processes. Further, the manufacturing requires lessphotolithography processes using a mask, thus reducing equipment outlayfor the photolithography. On this account, it is possible to reduce thetime and costs of manufacturing.

Note that, in addition to the foregoing inkjet method, the dropping ofthe droplet of a semiconductor material, a resist material or aconductive material can be carried out by any methods enabling directformation of the semiconductor layer, the resist layer or the conductorforming layer, by dropping a droplet(s).

A manufacturing method of a TFT array substrate according to the presentinvention includes the steps of: (a) forming a gate electrode on asubstrate; (b) forming a gate insulation layer on the gate electrode;(c) depositing a semiconductor film on the gate insulation layer; (d)forming a resist layer having a shape of a droplet by dropping a dropletof a resist material on the semiconductor film; and (e) removing theresist layer, after processing the semiconductor film corresponding tothe shape of the resist layer so as to create a semiconductor layer of athin film transistor section.

In this manner, a resist layer is formed on a deposited semiconductorfilm by dropping a droplet of a resist material, and the semiconductorlayer is formed by using this resist layer having the shape of thedroplet (normally a circular shape) as a mask.

With this method, it is possible to manufacture the TFT array substratewithout a mask for forming a semiconductor layer. Accordingly, therequired number of masks in the manufacturing is reduced, thus reducingmanufacturing processes. Further, the manufacturing requires lessphotolithography processes using a mask, thus reducing equipment outlayfor the photolithography. On this account, it is possible to reduce thetime and costs of manufacturing.

Note that, in addition to the foregoing inkjet method, the dropping ofthe droplet of a resist material can be carried out by any methodsenabling direct formation of the resist layer by dropping a droplet(s).

A manufacturing method of a TFT array substrate according to the presentinvention includes the steps of: (a) forming a gate electrode with abranch electrode on a substrate; (b) forming a gate insulation layer onthe gate electrode; and (c) forming a semiconductor layer having a shapeof a droplet as a semiconductor layer of a thin film transistor section,by dropping a droplet of a semiconductor material on the gate insulationlayer on the branch electrode.

In this manner, the semiconductor layer is formed in a shape of adroplet (normally a circular shape) by only dropping a droplet of asemiconductor material on the gate insulation layer of the branchelectrode.

With this method, it is possible to manufacture the TFT array substratewithout a mask for forming a semiconductor layer. Accordingly, therequired number of masks in the manufacturing is reduced, thus reducingmanufacturing processes. Further, the manufacturing requires lessphotolithography processes using a mask, thus reducing equipment outlayfor the photolithography. On this account, it is possible to reduce thetime and costs of manufacturing, and to effectively use the materials.

Note that, in addition to the foregoing inkjet method, the dropping ofthe droplet of a semiconductor material can be carried out by anymethods enabling direct formation of the semiconductor layer by droppinga droplet(s).

A manufacturing method of a TFT array substrate according to the presentinvention includes the steps of: (a) forming a gate electrode on asubstrate; (b) forming a gate insulation layer on the gate electrode;(c) forming a semiconductor layer of a thin film transistor section onthe gate insulation layer; (d) forming a first area to which a sourceelectrode is formed, and a second area to which at least a pixelelectrode is formed, by dropping a droplet of an electrode material onthe substrate after subjected to the step (c); and (e) forming a sourceelectrode, a drain electrode, and a pixel electrode in the first and thesecond areas by dropping droplets of an electrode material on thesubstrate after subjected to the step (d).

In this manner, the first area to which a source electrode is formed bydropping a droplet of an electrode material, and the second area towhich at least a pixel electrode is formed by dropping a droplet of anelectrode material are formed in one process for pre-processing of theelectrode forming step. Therefore, the manufacturing processes and costscan be reduced compared to the case of separately forming the first andthe second areas in different steps.

A manufacturing method of a liquid crystal display device according tothe present invention includes one of the foregoing manufacturingmethods of a TFT array substrate. Therefore, it is possible to reduce atleast manufacturing processes for producing a liquid crystal displaydevice, thus reducing costs.

A TFT array substrate according to the present invention includes: athin film transistor section in which a gate electrode is formed on asubstrate, and a semiconductor layer and a conductor layer are formed onthe gate electrode via a gate insulation layer, wherein: the conductorlayer is formed in contact with the semiconductor layer and one ofsource and drain electrodes of the thin film transistor section, and hasa portion formed by dropping a droplet, the conductor layer and thesemiconductor layer having substantially the same shape in the portionformed by dropping a droplet.

In this arrangement, a conductor forming layer is formed on a depositedsemiconductor film by dropping a droplet of a conductive material, andthe semiconductor layer is formed by using this conductor forming layerhaving the shape of the droplet (normally a circular shape). Theconductor forming layer is then processed to be completed as a conductorlayer. This conductor forming layer is used as a mask for forming thesemiconductor layer, but is not required to be removed unlike the resistlayer; therefore, the removal process can be omitted. In thisarrangement, the dropping of the droplet of a conductive material ontothe semiconductor layer can be carried out by an inkjet method, forexample, or by any methods enabling formation of a droplet having anappropriate size for a semiconductor layer of the thin film transistorsection.

With this arrangement of a TFT array substrate, the semiconductor layercan be formed without a mask; and therefore the required number of masksis reduced. Further, the conductor forming layer is not required to beremoved unlike the resist layer, and therefore the removal process canbe omitted, thus greatly reducing manufacturing processes. Further, themanufacturing can be performed with less number of photolithographyprocesses using a mask, thus reducing equipment outlay forphotolithography. Moreover, the required amount of chemicals, such as adeveloper or removing agent can also be reduced, as well as amount ofwaste of the resist material etc. On this account, it is possible toreduce the time and costs of manufacturing.

Further, the conductor layer may be constituted of Mo, W, Ag, Cr, Ta,Ti, a metal material mainly containing one of Mo, W, Ag, Cr, Ta, Ti, oran indium tin oxide.

Here, the metal material mainly containing one of Mo, W, Ag, Cr, Ta, Timay be an alloy material, or may be one containing a nonmetallicelement, such as N, O, or C. Since the diffusion amount of thesematerials to the semiconductor layer is small, these material examplesof the conductor layer shown here are used as a diffusion preventinglayer.

More specifically, with the foregoing arrangement, the conductor layer,provided between the semiconductor layer and the source or drainelectrode, operates as a diffusion preventing layer for practicallypreventing diffusion of a component element(s) constituting the sourceelectrode or the drain electrode. Further, the conductor forming layer,which is a previous state of the conductor layer, also operates as thediffusion preventing layer. Here, practical prevention of diffusionrefers to an effect that the diffusion amount of the materials is sosmall even after heat treatment that there is few practical influence ofthe diffusion to the semiconductor layer.

With this arrangement, manufacturing processes can be greatly reducedcompared to the conventional method for forming a diffusion preventinglayer after the semiconductor layer, for example, a method in which thesource and drain electrodes are respectively constituted of a diffusionpreventing layer and a low electric resistance layer, in this order fromthe glass substrate.

In recent years, demand for a larger TFT array substrate requiresgreater low electric resistance of a source or drain electrode, andtherefore a source or drain electrode is often made of Al, Cu or thelike, which is likely to diffuse into the semiconductor layer when thematerial is directly in contact with the semiconductor layer. Theforegoing configuration of the present invention can deal with such acircumstance. Therefore, the configuration of the present invention hasa wider selection range of materials for constituting a source or drainelectrode, while hardly increasing the number of manufacturingprocesses.

In the TFT array substrate according to the present invention having theforegoing configuration, by constituting the conductor layer with theforegoing method, the conductor forming layer as a previous state of theconductor layer operates as a pattern mask for forming the semiconductorlayer and also as a diffusion preventing layer for preventing thediffusion into the semiconductor layer. Furthermore, the conductor layercreated from the conductor forming layer also has the diffusionpreventing function. Accordingly, the manufacturing processes can begreatly reduced when the source electrode etc. is made of a materialsuch as Al, Cu, which tends to diffuse into the semiconductor layer,thus improving productivity of the TFT array substrate.

The source and drain electrodes are preferably made of an Al or a metalmaterial mainly containing Al.

Here, the metal material mainly containing Al may be an Al alloymaterial, such as an Al—Ti or Al—Nd, or may be one containing anonmetallic element, such as N, O, or C.

The conductor forming layer of the present invention is divided to bethe conductive layers through partial etching using patterns of thesource and drain electrodes. This process is necessary to electricallydivide the source and drain electrodes of the TFT.

With the foregoing arrangement, it is possible to subject the conductorforming layer to wet-etching while hardly damaging the areas of thesource and drain electrodes.

This wet-etching uses a characteristic of an Al or the metal materialmainly containing Al, which is not likely to be damaged by an oxidativeacid, such as a nitric acid.

Here, the conductor forming layer is preferably made of an Ag, Mo, W, oran alloy mainly containing an Ag, Mo, W, which are soluble by anoxidative acid such as a nitric acid. With this arrangement, theconductor forming layer can be subjected to wet-etching by an oxidativeacid, such as a nitric acid with desirable selectivity, thus obtainingthe conductor layer without hardly damaging the source electrode etc.made of an Al or the metal material mainly containing Al.

The TFT array substrate according to the present invention having theforegoing configuration includes a low resistance source electrode etc.made of an Al or the metal material mainly containing Al. Therefore theTFT array substrate can be compatible with a recent large-sized TFTarray substrate.

The TFT array substrate according to the present invention isexceptionally useful because it has the foregoing configuration with twocharacteristics: low electrical resistance and appropriateness ofmanufacturing process which enables etching of the conductor forminglayer to create a conductor layer with desirable selectivity.

Note that, in addition to the foregoing inkjet method, the dropping ofthe droplet of a conductive material can be carried out by any methodsenabling direct formation of the conductor forming layer by dropping adroplet(s).

Further, the liquid crystal display device according to the presentinvention includes the foregoing TFT array substrate. Accordingly, themanufacturing of the liquid crystal display device requires lessmanufacturing steps of the TFT array substrate, thus reducing the timeand costs of manufacturing.

Such a TFT array substrate can be manufactured through the followingmethod, for example.

A manufacturing method of a TFT array substrate according to the presentinvention includes the steps of: (a) forming a gate electrode on asubstrate; (b) forming a gate insulation layer on the gate electrode;(c) depositing a semiconductor film on the gate insulation layer; (d)forming a conductor forming layer having a shape of a droplet bydropping a droplet of a conductive material on the semiconductor film;and (e) forming a semiconductor layer of a thin film transistor sectionby processing the semiconductor film corresponding to the shape of theconductor forming layer.

In this arrangement, a conductor forming layer is formed on a depositedsemiconductor film by dropping a droplet of a conductive material, andthe semiconductor layer is formed by using this conductor forming layerhaving the shape of the droplet (normally a circular shape) as a mask.This conductor forming layer is not required to be removed unlike theresist layer; therefore, the removal process can be omitted.

With this arrangement of a TFT array substrate, the semiconductor layercan be formed without a mask; and therefore the required number of masksis reduced, thus reducing manufacturing processes. Further, themanufacturing can be performed with less number of photolithographyprocesses using a mask, thus reducing equipment outlay forphotolithography. Further, the required amount of chemicals, such as adeveloper or removing agent can also be reduced, as well as amount ofwaste of the resist material etc. On this account, it is possible toreduce the time and costs of manufacturing.

Note that, in addition to the foregoing inkjet method, the dropping ofthe droplet of a conductive material can be carried out by any methodsenabling direct formation of the conductor forming layer by dropping adroplet(s).

Further, the conductor layer may be constituted of Mo, W, Ag, Cr, Ta,Ti, a metal material mainly containing one of Mo, W, Ag, Cr, Ta, Ti, oran indium tin oxide.

Further, the source and drain electrodes may be made of an Al or a metalmaterial mainly containing Al.

The manufacturing method of a liquid crystal display device according tothe present invention includes one of the foregoing manufacturingmethods of a TFT array substrate. Therefore, it is possible to reduce atleast manufacturing processes for producing a liquid crystal displaydevice.

Further, the TFT array substrate of the present invention is compatiblewith various electronic devices as well as a liquid crystal displaydevice. The various electronic devices may be some different types ofelectronic device using a TFT array substrate; for example, a displaydevice such as an organic EL panel or an inorganic EL panel; or atwo-dimensional image input device such as a fingerprint sensor or anX-ray imaging device.

Additional objects, features, and strengths of the present inventionwill be made clear by the description below. Further, the advantages ofthe present invention will be evident from the following explanation inreference to the drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1(a) is a plan view showing a schematic configuration of a pixel ofa TFT array substrate in a liquid crystal display device according toone Embodiment of the present invention.

FIG. 1(b) is a cross-sectional view, taken along the line A-A of FIG.1(a).

FIG. 2 is a perspective view schematically showing a pattern formingequipment using an inkjet method, and is used for manufacturing of aliquid crystal display device according to one Embodiment of the presentinvention.

FIG. 3 is a flow chart showing manufacturing steps of the TFT arraysubstrate shown in FIG. 1.

FIG. 4(a) is a plan view of a TFT array substrate for explaining thegate line pre-processing step shown in FIG. 3.

FIG. 4(b) is a plan view of a TFT array substrate for explaining thegate line applying/forming step shown in FIG. 3.

FIG. 4(c) is a cross-sectional view, taken along the line B-B of FIG.4(b).

FIGS. 5(a) through 5(c) are cross-sectional views corresponding to aportion taken along the line B-B of FIG. 4(b), and FIG. 5(a) shows thegate insulation layer/semiconductor layer depositing step, FIG. 5(b)shows how a thermosetting resin is formed on the semiconductor layer inthe semiconductor layer forming step shown in FIG. 3, FIG. 5(c) shows anetching process of the a-Si forming layer and the n+ forming layer inthe same step, and FIG. 5 (d) is a cross-sectional view, taken along theline C-C of FIG. 5(e), showing a resist removal process in the samestep, and FIG. 5(e) is a plan view of a TFT array substrate after thesemiconductor layer forming step.

FIG. 6(a) is a plan view of a TFT array substrate for explaining thesource/drain lines pre-processing step shown in FIG. 3.

FIG. 6(b) is a plan view of a TFT array substrate for explaining thesource/drain lines applying/forming step.

FIG. 6(c) is a cross-sectional view, taken along the line D-D of FIG.6(b).

FIG. 7 is a plan view showing a TFT section in the TFT array substrateshown in FIG. 1(a).

FIGS. 8(a) and 8(b) are cross-sectional views corresponding to a portiontaken along the line D-D of FIG. 6(b), and FIG. 8(a) shows removalprocess of wiring guide in the channel section processing step shown inFIG. 3, and FIG. 8(b) shows oxidation treatment of the n+ layer in thesame step.

FIG. 9(a) is a plan view of a TFT array substrate for explaining thepassivation film forming step and the passivation film processing step,which are shown in FIG. 3.

FIG. 9(b) is a cross-sectional view, taken along the line E-E of FIG.9(a).

FIG. 10(a) is a plan view of a TFT array substrate for explaining thepixel electrode forming step shown in FIG. 3.

FIG. 10(b) is a cross-sectional view, taken along the line F-F of FIG.10(a).

FIGS. 11(a) and 11(b) are explanatory views showing mechanism ofoccurrence of a leak current in the TFT section shown in FIG. 1(a), andFIG. 11(a) is a plan view showing the TFT section with the gateelectrode penetrating through the semiconductor pattern, and FIG. 11(b)is a cross-sectional view, taken along the line G-G of FIG. 11(a).

FIG. 12(a) is a plan view of the TFT section in which the gate electrodedoes not penetrate through the semiconductor pattern, in contrast to theconfiguration of FIG. 11(a), for showing the mechanism of occurrence ofa leak current.

FIG. 12(b) is a cross-sectional view, taken along the line H-H of FIG.12(a).

FIG. 13 is a plan view showing the TFT section shown in FIG. 1(a) whenthe a-Si layer is not balanced with respect to the gate electrode.

FIG. 14(a) is a vertical cross-sectional view for explaining amanufacturing method of the TFT array substrate having an upper lightblocking film in addition to a lower light blocking film, and shows astate of the TFT array substrate when a partial oxidation treatment ofthe channel section is completed.

FIG. 14(b) is a vertical cross-sectional view of the TFT array substrateshowing the step for forming an upper light blocking film.

FIG. 14(c) is a cross-sectional view, taken along the lines M-M of FIG.14(d).

FIG. 14(d) is a plan view of the TFT array substrate showing a statewhere forming of a pixel electrode is completed.

FIG. 15(a) is a plan view showing a schematic configuration of a pixelof a TFT array substrate in a liquid crystal display device according toanother Embodiment of the present invention.

FIG. 15(b) is a cross-sectional view, taken along the line I-I of FIG.15(a).

FIG. 16 is a flow chart showing manufacturing steps of the TFT arraysubstrate shown in FIGS. 15(a) and 15(b).

FIG. 17 is a plan view of a TFT array substrate for explaining thesource and drain/pixel electrodes pre-processing step shown in FIG. 16.

FIG. 18(a) is a plan view of a TFT array substrate for explaining thesource line applying/forming step shown in FIG. 16.

FIG. 18(b) is a cross-sectional view, taken along the line J-J of FIG.18(a).

FIG. 19(a) is a plan view for explaining the drain/pixel electrodesapplying/forming step shown in FIG. 16.

FIG. 19(b) is a cross-sectional view, taken along the line K-K of FIG.19(a).

FIGS. 20(a) and 20(b) are cross-sectional views corresponding to aportion taken along the line K-K of FIG. 19(a), and FIG. 20(a) showsremoval process of a wiring guide in the channel section processing stepshown in FIG. 16, and FIG. 20(b) shows an oxidation treatment of the n+layer in the same step.

FIG. 21 is a cross-sectional view corresponding to a portion taken alongthe line K-K of FIG. 19(a) for explaining the passivation film formingstep shown in FIG. 16.

FIG. 22(a) is a cross-sectional view showing a TFT array substrateaccording to still another Embodiment of the present invention, andshows a state of the TFT array substrate before provided with asemiconductor layer.

FIG. 22(b) is a cross-sectional view, taken along the line L-L of FIG.22(c), showing the TFT array substrate provided with a semiconductorlayer.

FIG. 22(c) is a plan view showing the TFT array substrate provided witha semiconductor layer.

FIG. 23 is a plan view showing a schematic configuration of a pixel of aTFT array substrate in a liquid crystal display device according to yetanother Embodiment of the present invention.

FIG. 24 is an explanatory view showing a droplet having substantially around shape, as an example of the shape of droplet dropped from thepattern forming equipment shown in FIG. 2.

FIG. 25 (a) is an explanatory view showing a droplet having asubstantially circular shape by being deformed from a circle, as anotherexample of the shape of the droplet shown in FIG. 24.

FIG. 25(b) is an explanatory view showing a shape having a concaveportion.

FIG. 25(c) is an explanatory view showing a shape partly including aconvex portion.

FIG. 26(a) shows a case where an irregular oval shape is formed by twodroplets.

FIG. 26(b) is an explanatory view showing a shape formed by threedroplets.

FIG. 27 (a) is an explanatory view showing a state, which is not desiredin the present invention, where plural infinitesimal droplets aredropped.

FIG. 27(b) is an explanatory view showing a shape formed by the state ofFIG. 27(a).

FIG. 28 is a flow chart showing manufacturing steps of a TFT arraysubstrate for a conventional liquid crystal display device.

FIG. 29 is a graph showing a TFT characteristic of a TFT array substrateaccording to the present invention.

FIG. 30 is a magnified view of a TFT section of a TFT array substrate,with the gate electrode having an open end not penetrating through thesemiconductor layer.

FIG. 31 is a magnified view of a TFT section of a TFT array substrate,with the gate electrode having an open end penetrating through thesemiconductor layer.

FIG. 32 is a magnified view of a TFT section of a TFT array substrate,with the gate electrode having an open end penetrating through thesemiconductor layer.

FIG. 33 is a plan view showing a schematic configuration of a pixel of aTFT array substrate in a liquid crystal display device according afurther Embodiment of the present invention.

FIG. 34 is a plan view showing a schematic configuration of a pixel of aTFT array substrate in a liquid crystal display device according a stillfurther Embodiment of the present invention.

FIG. 35 is a magnified view of the main part of a pixel in the TFT arraysubstrate shown in FIG. 33.

FIG. 36 is a magnified view of the main part of a pixel in the TFT arraysubstrate shown in FIG. 34.

FIG. 37 is an explanatory view for regulating the relation between anopen end of the gate electrode in the TFT section and the border linearea of the semiconductor layer.

FIG. 38 is another explanatory view for regulating the relation betweenthe open end of the gate electrode in the TFT section and the borderline area of the semiconductor layer.

FIG. 39(a) is a plan view showing a schematic configuration of a pixelof a TFT array substrate in a liquid crystal display device according ayet further Embodiment of the present invention.

FIG. 39(b) is a cross-sectional view, taken along the line M-M of FIG.39(a).

FIG. 40 is a flow chart showing manufacturing steps of the TFT arraysubstrate shown in FIGS. 39(a) and 39(b).

FIG. 41(a) is a cross-sectional view corresponding to a portion takenalong the line N-N of FIG. 41(d), showing a condition ready for the gateinsulation layer/semiconductor layer depositing step shown in FIG. 40.

FIG. 41(b) is a cross-sectional view corresponding to a portion takenalong the line N-N of FIG. 41(d), showing a condition during thesemiconductor layer forming step shown in FIG. 40.

FIG. 41(c) is a cross-sectional view, taken along the line N-N of FIG.41(d), showing completion of the gate insulation layer/semiconductorlayer depositing step shown in FIG. 40.

FIG. 41 (d) is a plan view of a glass substrate after the semiconductorlayer forming step.

FIG. 42(a) is a plan view of a TFT array substrate for explaining thesource/drain lines pre-processing step shown in FIG. 40.

FIG. 42(b) is a plan view of a TFT array substrate for explaining thesource and drain lines applying/forming step.

FIG. 42(c) is a cross-sectional view, taken along the line O-O of FIG.42(b).

FIGS. 43(a) through 43(c) are cross-sectional views corresponding to aportion taken along the line O-O of FIG. 42(b), and FIG. 43(a) showsremoval process of wiring guide in the channel section processing stepshown in FIG. 40, FIG. 43(b) shows a partial etching process of aconductor forming layer in the same step, and FIG. 43(c) shows partialoxidation treatment of the n+ layer in the same step.

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

One Embodiment of the present invention is described below withreference to FIGS. 1 through 13.

A liquid crystal display device according to the present Embodimentincludes a pixel shown in FIG. 1(a). Note that, FIG. 1(a) is a plan viewshowing a schematic configuration of a pixel of a TFT array substrate inthe liquid crystal display device. Further, FIG. 1(b) is across-sectional view, taken along the line A-A of FIG. 1(a).

As shown in FIGS. 1(a) and 1(b), a TFT array substrate 11 is made of aglass substrate 12 on which a gate electrode 13 and a source electrode17 are aligned in a matrix manner. A storage capacitor electrode 14 isprovided between two adjacent gate electrodes 13.

As shown in FIG. 1(b), in the TFT array substrate 11, the gate electrode13 and the storage capacitor electrode 14 are provided on the glasssubstrate 12 in an area between a TFT section 22 and an storagecapacitor section 23; and a gate insulation layer 15 is further providedthereon.

Further, a semiconductor layer 16 including an a-Si layer is formed onthe gate electrode 13 via the gate insulation layer 15, and the sourceelectrode 17 and a drain electrode 18 are further formed thereon. Oneend of the drain electrode 18 extends to an area on the storagecapacitor electrode 14 by having the gate insulation layer 15underneath, and a contact hole 24 is formed on this area. A passivationfilm 19 is formed on the source electrode 17 and the drain electrode 18,and a photosensitive acrylic resin layer 20 and a pixel electrode 21 arefurther formed thereon in this order.

In the present Embodiment, manufacturing of the TFT array substrate 11is performed with a pattern forming equipment. This pattern formingequipment discharges or drops material of the layer with an inkjetmethod, for example.

As shown in FIG. 2, the pattern forming equipment includes a supportingstage 32 on which a substrate 31 (corresponding to the glass substrate12) is placed. The pattern forming equipment includes an inkjet head 33as droplet discharging means for discharging, for example, fluid ink(droplet) containing a wiring material, with respect to the surface ofthe substrate 31 placed on the supporting stage 32, and an X-directiondriving section 34 for moving the inkjet head 33 in the X-direction, asdenoted in the figure, and a Y-direction driving section 35 for movingthe inkjet head 33 in the Y-direction of the figure.

Further, the pattern forming equipment includes an ink supplying system36 for supplying ink to the inkjet head 33, and also includes a controlunit 37. The control unit 37 performs various controls including drivingcontrol for the X-direction driving section 34 and the Y-directiondriving section 35, and discharge control for the inkjet head 33. Thecontrol unit 37 supplies information for indicating the position wherethe ink is applied, with respect to the X and Y-direction drivingsections 34 and 35, and supplies discharge information to a head driver(not shown) of the inkjet head 33. With this arrangement, the inkjethead 33 is shifted by the X-direction driving section 34 and Y-directiondriving section 35 so that the substrate 31 is provided with desiredamount of droplet in a target position on its surface.

The inkjet head 33 may be of a piezo-type using a piezoactuator, abubble-type including a heater in the head, or the like. The dischargeamount of the inkjet head 33 may be controlled according to anapplication voltage. Further, the droplet discharging means may be anymeans capable of supplying a droplet; therefore, the inkjet head 33 mayinstead be a device having only a droplet dropping function, forexample.

Next, the following will explain a manufacturing method of the TFT arraysubstrate 11 for a liquid crystal display device according to thepresent invention.

In the present Embodiment, the TFT array substrate 11 is manufacturedthrough, as shown in FIG. 3, a gate line pre-processing step 41, a gateline applying/forming step 42, a gate insulation layer/semiconductorlayer depositing step 43, a semiconductor layer forming step 44, asource/drain lines pre-processing step 45, a source/drain linesapplying/forming step 46, a channel section processing step 47, apassivation film forming step 48, a passivation film processing step 49,and a pixel electrode forming step 50.

[Gate Line Pre-Processing Step 41]

The gate line pre-processing step 41 is performed as a pre-processing ofthe gate line applying/forming step 42. The gate line applying/formingstep 42 as the following step is performed for forming a gate electrode13, an storage capacitor electrode 14 etc. by dropping liquid wiringmaterial with a pattern forming equipment. Therefore, this step carriesout preparation for appropriate liquid wiring material application,i.e., appropriate discharging (dropping) of the liquid wiring materialfrom a pattern forming equipment with respect to a gate line formingarea 61 and an storage capacitor electrode forming area 63 shown in FIG.4(a). Note that, FIG. 4(a) is a plan view of a glass substrate 12included in the TFT array substrate 11.

This step falls roughly into two processes. In hydrophilic/hydrophobicprocessing (lyophilic/lyophobic processing) as the first process, thesubstrate is provided with either lyophilic characteristic or lyophobiccharacteristic with respect to the liquid wiring material, so as topattern a hydrophilic (lyophilic) area as an area for forming the gateline 61 etc., and a hydrophobic (lyophobic) area as an area for notforming such electrodes. In a guide forming process as the second step,the substrate is provided with guides along the gate line forming area61 etc., for controlling flow of the liquid.

The first step, i.e., the hydrophilic/hydrophobic processing istypically performed by a photocatalyst containing titanium oxide. Thesecond step, i.e., the guide forming is performed by photolithographyusing a resist material. Occasionally, the guide or the surface of thesubstrate may be exposed to CF₄/O₂ plasma so as to obtainhydrophilic/hydrophobic characteristics. The resist is removed after thewiring is formed.

In the present Embodiment, the hydrophilic/hydrophobic processing wasperformed by a photocatalyst using titanium oxide, as described below.

The glass substrate 12 of the TFT array substrate 11 was coated with aZONYL FSN (Product Name: provided by Dupont-TORAY Co. ltd), which is afluorochemical nonionic surfactant which had been mixed with anisopropyl alcohol. Further, a mask of the pattern for the gate electrode13 etc. was provided with a photocatalyst layer by subjecting the maskspin-coating with a mixture containing titanium dioxide particledispersing element and an ethanol, and then by baking the mask at 150°.Next, the glass substrate 12 was exposed to ultraviolet light with themask. This exposure was performed for two minutes using irradiation ofultraviolet light of 365 nm on condition of 70 mW/cm².

Here, when it is predicted that the semiconductor layer 16 on the glasssubstrate 12 is exposed to intensive light, a light blocking film 62 maybe formed in advance, as shown in FIG. 4(a), so as to prevent thesemiconductor layer 16 from the light. The light blocking film 62 isformed by dropping the material of film by a pattern forming equipmentwith respect to a position where an a-Si layer is formed, and then bybaking the dropped material. This material of the film may be aphotosensitive resin or a thermosetting resin, which is mixed with ablack colored material such as a carbon black or TiN.

Note that, for ease of explanation, the electrode for forming the TFT,which is branched out of the gate electrode, is omitted in the uppergate electrode of FIG. 4 and later drawings.

[Gate Line Applying/Forming Step 42]

FIGS. 4(b) and 4(c) show the gate line applying/forming step 42. FIG.4(b) is a plan view of the glass substrate 12 provided with the gateelectrode 13, and FIG. 4(c) is a cross-sectional view, taken along theline B-B of FIG. 4(b).

In this step, as shown in FIGS. 4(b) and 4(c), a material of wiring isapplied onto the gate line forming area 61 and the storage capacitorelectrode forming area 63 on the glass substrate 12 with a patternforming equipment. In this Embodiment, an organic solvent in which Agparticles coated with an organic film are dispersed was used as thewiring material. The wiring width was adjusted to approximately 50 μm,and discharge amount of the wiring material from the inkjet head 33 wasadjusted to 80 pl.

In the area processed to have hydrophilic/hydrophobic characteristics,the wiring material discharged from the inkjet head 33 spreads along thegate line forming area 61, and therefore, the space between eachdischarging of the wiring material was adjusted to approximately 500 μm.After the discharging, the material was baked for an hour with a bakingtemperature of 350° C. so as to complete the wiring of the gateelectrode 13.

Note that, the baking temperature of 350° C. in this example wasdetermined in consideration of the coming semiconductor layer formingstep 44 in which processing heat of about 300° C. will be added. Thus,the baking temperature is not limited to this temperature. For example,in case of forming an organic semiconductor, the baking temperature maybe decreased to a range from 200 to 250° C., if the annealingtemperature is set to 100 to 200° C.

Further, in addition to Ag, the wiring material may also be Ag—Pd,Ag—Au, Ag—Cu, Cu, Cu—Ni etc. These materials may be individuallyadopted, or in a form of particles of an alloy material, or as a pastedissolved in an organic solvent. Further, each dissociation temperatureof the coating layer on the surface of the particles and the organicmaterial dissolved in the solvent may be controlled according to therequired baking temperature so that the wiring material has a desiredresistance value and surface condition. Note that, the dissociationtemperature designates a temperature for causing vaporization of thecoating layer on the surface and the solvent.

[Gate Insulation Layer/Semiconductor Layer Depositing Step 43]

FIG. 5(a) shows the gate insulation layer/semiconductor layer depositingstep 43. In this step, the gate insulation layer 15, the a-Si forminglayer 64, and the n+ forming layer 65 are continuously formed in thisorder on the glass substrate 12, which has been through the gate lineapplying/forming step 42. In this Embodiment, the a-Si forming layer 64was made by a CVD method. The thicknesses of the gate insulation layer15, the a-Si forming layer 64, and the n+ forming layer 65 are set to0.3 μm, 0.15 μm, and 0.04 μm, respectively, and each layer was formedcontinuously without taking the substrate from the vacuum equipment. Thedeposition temperature was 300° C.

[Semiconductor Layer Forming Step 44]

FIGS. 5(b) through 5(e) show the semiconductor layer forming step 44.FIG. 5(e) is a plan view showing the glass substrate 12 after thesemiconductor layer forming step 44, FIG. 5 (d) is a cross-sectionalview, taken along the line C-C of FIG. 5(e), and FIGS. 5(b) and 5(c) arecross-sectional views showing respective processes in the portion ofFIG. 5(d).

In this step, as shown in FIG. 5(b), a thermosetting resin as the resistmaterial was dropped from a pattern forming equipment onto the n+forming layer 65 in a portion right above a TFT section gate electrode(branch electrode) 66, which is branched out from the main line of thegate electrode 13. The resin thus applied by dropping was then formed tobe a resist layer 67, which is used as a processing pattern. Thedischarging amount of the resist material was a 10 pl droplet. As aresult, a circular pattern with a diameter=30 μm was formed on apredetermined position above the TFT section gate electrode 66. Then thepattern was baked with the baking temperature of 150° C. As to thethermosetting resin for forming the resist layer 67, the presentEmbodiment used a resist of TEF series (provided by Tokyo Ohka Kogyo co.ltd.) whose viscosity had been adjusted in advance to be used for aninkjet method.

Note that, in addition to the thermosetting resin, an UV resin or aphotoresist may also be used as the material of the resist layer 67.Further, though it is not a required condition, a transparent resistlayer 67 makes positioning upon forming easier. Further, it ispreferable that the resist layer 67 is resistant to the heat uponetching, resistant to dry etching gas, and has good selectivity toetching materials.

Next, as shown in FIG. 5(c), the n+ forming layer 65 and the a-Siforming layer 64 were subjected to dry etching using a gas (such asSF₆+HCl) so as to form an n+ layer 69 and an a-Si layer 68. Thereafter,the glass substrate 12 was washed by an organic solvent, and the resistlayer 67 was removed, as shown in FIG. 5(d).

As described, in the semiconductor layer forming step 44, the resinpattern (the pattern of the resist layer 67) discharged from a patternforming equipment determines the shape of the semiconductor layer 16which is made up of the n+ layer 69 and the a-Si layer 68. Namely, thesemiconductor layer 16 is formed as a circular or substantially acircular pattern made up of a curved line, according to the shape of thematerial of the resist layer 67 dropped on the glass substrate 12 fromthe inkjet head 33.

Though the resist layer 67 of this embodiment is formed by s singledroplet with a pattern forming equipment, the resist layer 67 may alsobe formed by plural droplets. However, it should be noted that, when theresist layer 67 is formed by a plurality of extremely small droplets,forming of a semiconductor layer 16 takes a long period of time, andalso the life of the inkjet head 33 is shortened as more dot number isrequired.

When forming a desirable size of layer (film) by dropping droplets withthe inkjet head 33, it is important to drop an appropriate amount ofdroplet with a minimum number of shots. In this way, it is possible tocarry out maximum number of processings within the life period of theinkjet head 33, thus minimizing device cost.

Further, as another noticeable characteristic of the semiconductor layerforming step 44, no particular processing is necessary for the surfaceto be supplied with droplets discharged from the inkjet head 33. Morespecifically, if the surface to be supplied with droplets issignificantly hydrophilic, the discharged droplet will spread in aninfinite form unless the surface is patterned. In such a condition, thefilm forming cannot be performed. However, since it contains a largenumber of Si dangling bonds, the a-Si forming layer 64 is basicallyhydrophobic. Therefore, the droplet is applied on the a-Si forming layer64 with a certain large degree of contact angle, and results in asubstantially circular shape. Accordingly, no particular processing isrequired for the substrate (a-Si forming layer 64).

Further, a substrate which has been subjected to baking or processing ina gas (dry etching) etc. often has substances in a form of a shortmolecular on its surface. Therefore, the discharged droplet is likely toforms a certain large degree of contact angle, even when using othersemiconductor than a-Si, such as an organic semiconductor.

Conventionally, patterning of a semiconductor layer requires a mask andphotolithography processing. However, in the semiconductor layer formingstep 44, the mask pattern is directly drawn with a droplet dropped fromthe inkjet head 33, thus not requiring a mask and photolithographyprocessing. Therefore, by adopting this step, manufacturing cost can begreatly reduced.

[Source/Drain Lines Pre-Processing Step 45]

FIG. 6(a) shows the source/drain lines pre-processing step 45. FIG. 6(a)is a plan view showing the glass substrate 12 which has been through thesemiconductor layer forming step 44, and provided with a wiring guide 71for forming the source and drain electrodes 17 and 18.

In this step, the wiring guide 71 is formed on an area (source/drainforming area 73) on which the source electrode 17 and the drainelectrode 18 and the drain electrode 18 will be formed. In thisEmbodiment, the wiring guide 71 was formed by a photoresist material.More specifically, the glass substrate 12 after the semiconductor layerforming step 44 was coated with a photoresist, subjected to pre-baking,exposed using a photo mask, developed, and then subjected topost-baking. The wiring guide 71 thus created had a width =10 μm, andthe width of the groove (the width of the wiring forming area) createdwith the wiring guide 71 was approximately 15 μm. Note that, theinterval between the source and drain electrodes, i.e., the channelsection 72 was set to 4 μm.

Note that, here, the glass substrate 12 may be arranged such that theSiNx surface (the upper surface of the gate insulation layer 15) isprocessed to have hydrophilicity by an oxygen plasma, and the wiringguide 71 is processed to have water-repellence by exposing to CF₄plasma, so that the wiring material from a pattern forming equipment canbe smoothly applied to the base surface.

Further, instead of forming the wiring guide 71, the glass substrate 12may be subjected to the hydrophilic/hydrophobic processing using aphotocatalyst according to the pattern of wiring electrode, as with theforegoing gate electrode forming step.

[Source/Drain Lines Applying/Forming Step 46]

FIGS. 6(b) and 6(c) show the source/drain lines applying/forming step46. FIG. 6(b) is a plan view showing the source and drain electrodes 17and 18 which are formed along the wiring guide 71, and FIG. 6(c) is across-sectional view, taken along the line D-D of FIG. 6(b).

As shown in FIGS. 6(b) and 6(c), in this source/drain linesapplying/forming step 46, the source electrode 17 and the drainelectrode 18 were formed by coating the source/drain forming area 73,which is formed by the wiring guide 71, with a wiring material by usinga pattern forming equipment. Here, the discharging amount of the wiringmaterial from the inkjet head 33 was set to 2 pl. Further, Ag particlesare used as the wiring material, and the thicknesses of the electrodeswere adjusted to 0.3 μm. Further, baking temperature was 200° C., andafter the baking, the wiring guide 71 was removed by an organic solvent.

Note that, in this step, the same wiring material may be used as the oneused for the gate electrode 13; however, the baking temperature isrequired to be at or lower than 300° C., since the a-Si is formed ataround 300° C.

Then, the basic structure of a TFT is almost completed by thus beingthrough the Gate line pre-processing step 41 through the source/drainlines applying/forming step 46.

Here, in the TFT section 22, it is important that the TFT gate electrode66 of the gate electrode 13 penetrates through the semiconductor pattern(a semiconductor layer 16) having substantially a circular shape, asshown in FIG. 7. In an arrangement in which the TFT section gateelectrode 66 is formed within the semiconductor pattern, a leak currentwill flow between the source and drain electrodes through asemiconductor area on which the electrical field from the TFT sectiongate electrode 66 does not sufficiently affect, even if the gate is OFF.This phenomenon will be described later in detail. Note that, in thepractical use of the TFT, the foregoing structure generates desirablephotoconductor even though the semiconductor pattern is extending out ofthe TFT section gate electrode 66, the source electrode 17, and thedrain electrode 18.

[Channel Section Processing Step 47]

This step is carried out for processing the channel section 72, as shownin FIGS. 8(a) and 8(b). FIGS. 8(a) and 8(b) are cross-sectional viewscorresponding to a portion taken along the line D-D of FIG. 6(b).Firstly, as shown in FIG. 8(a), the wiring guide 71 of the channelsection 72 was removed by an organic solvent or by ashing. Next, asshown in FIG. 8(b), the n+ layer 69 was subjected to oxidation treatmentby ashing or by using a laser so as to be a nonconductor.

[Passivation Film Forming Step 48, Passivation Film Processing Step 49]

FIGS. 9(a) and 9(b) show a state where the passivation film processingstep 49 is completed.

In this step, as shown in FIGS. 9(a) and 9(b), a SiO₂ film as apassivation film 19 was formed by a CVD on a glass substrate 12 whichhad been provided with the source and drain electrodes.

Next, the SiO₂ film was coated with an acrylic resist material so as tocreate a photosensitive acrylic resin layer 20, and then a pixelelectrode forming pattern (see FIG. 9(b)) and a terminal processingpattern were formed in this resist layer.

The pixel electrode pattern and the terminal processing pattern wereformed by a mask for creating a portion where the resist layer iscompletely removed, and a portion where the resist layer is removed by ahalf of the thickness, after the development. The latter portion is anarea for halftone exposure, whose transmittance of mask is 50%. Morespecifically, the resist layer is completely removed in the portion forforming a terminal by subjecting the passivation film 19 and the gateinsulation layer 15 to etching, and meanwhile, the resist layer isremoved to be half in thickness in the portion for forming a pixelelectrode 21 so as to create a guide with the photosensitive acrylicresin layer 20 in the periphery of the pixel electrode pattern. Next, byusing the resist layer as a mask, the passivation film 19 and the gateinsulation layer 15 in the terminal section were removed, and thepassivation film 19 in the portion for forming a pixel electrode 21 werepartly removed by etching.

[Pixel Electrode Forming Step 50]

As shown in FIGS. 10(a) and 10(b), the pixel electrode forming patternon the photosensitive acrylic resin layer 20 was coated with an ITOparticle material for creating a pixel electrode by using a patternforming equipment, and then was baked with a temperature of 200° C. soas to form a pixel electrode 21. Here, a TFT array substrate 11 iscompleted.

Conventional photolithography requires a mask in both the passivationfilm processing and an ITO processing, respectively. On the other hand,by carrying out halftone exposure with a photosensitive acrylic resin,those processings can be carried out with a single mask, thus reducingthe manufacturing cost.

Here, with reference to FIGS. 11(a) and 11(b), and FIGS. 12(a) and12(b), the following will explain the generation mechanism of a leakcurrent, which was mentioned in the source/drain lines applying/formingstep 46.

FIG. 11(a) is a plan view showing the TFT section with the TFT sectiongate electrode 66 penetrating through the semiconductor pattern(semiconductor layer 16), and FIG. 11(b) is a cross-sectional view,taken along the line G-G of FIG. 11(a). FIG. 12(a) is a plan viewshowing the TFT section with the TFT section gate electrode 66 notpenetrating through the semiconductor pattern and is provided within thesemiconductor pattern area. FIG. 12(b) is a cross-sectional view, takenalong the line H-H of FIG. 12(a). Further, FIGS. 11(a) and 12(a) show astate where a negative potential is applied to the gate electrode 13. Asshown in FIGS. 11(b) and 12(b), the TFT section gate electrode 66 andthe a-Si layer 68 are opposed to each other having the gate insulationlayer 15 therebetween. Here, the n+ layer. 69 is a layer to injectcarriers into the a-Si layer 68, and provided with an excessive numberof electrons through doping of such as a phosphorous (P).

For the respective TFTs shown in FIGS. 11(a) and 11(b) (the TFT sectiongate electrode 66 penetrating through the semiconductor pattern), andFIGS. 12(a) and 12(b) (the TFT section gate electrode 66 not penetratingthrough the semiconductor pattern), a voltage of −4V was applied to thegate electrode, and a leak current between the source and drainelectrodes were measured. The measurement came out as: the leak currentin the TFT section gate electrode 66 penetrating through thesemiconductor pattern was approximately 1 pA. Meanwhile, the leakcurrent in the TFT section gate electrode 66 not penetrating through thesemiconductor pattern increased to 30 to 50 pA.

The measurement was carried out under dark circumstances, and in thepresence of irradiation of a backlight, the leak current in the TFTsection gate electrode 66 penetrating through the semiconductor patternincreased to 20 pA. Meanwhile, the leak current in the TFT section gateelectrode 66 not penetrating through the semiconductor pattern greatlyincreased to approximately 2000 to 3000 pA. These results show that theTFT characteristic deteriorates in the arrangement with the TFT sectiongate electrode not penetrating through the semiconductor pattern.Further, reasons for those results may be explained as follows.

Firstly, the following will explain the case where a negative potentialis applied to the gate electrode 13. When a gate electrode is suppliedwith a negative potential, due to repulsive force between a negativecharge and a negative charge, carriers (electrons) are away from the TFTsection gate electrode 66, as shown in FIG. 11(a). Accordingly, theelectrons mostly exist in the vicinity of the source and drainelectrodes, and few electrons exist in the a-Si layer 68 of the channelsection. Thus, the TFT is OFF in this state. Even if the electrons goesfrom the gate toward the drain, they have to pass the TFT section gateelectrode 66. In this case, since the TFT section gate electrode 66 issupplied with a negative potential, the electrons cannot pass throughthe gate electrode due to repulsive force between a negative charge anda negative charge. Accordingly, a leak current is small in thisarrangement.

Meanwhile, in the arrangement shown in FIG. 12(a), in which the a-Silayer 68 extends beyond the front end portion of the TFT section gateelectrode 66, the electrons can move along the periphery of the a-Silayer 68 without passing through the TFT section gate electrode 66, evenwhen the gate electrode has negative potential. This allows the leakcurrent to easily flow. Further, in the presence of irradiation ofbacklight, carriers are generated due to excitation by the backlight.For the same reason above, these generated carriers can also flow alongthe periphery of the a-Si layer 68.

Therefore, upon backlight irradiation, the increase amount of the leakcurrent greatly varies between the arrangement of FIG. 11(a) with theTFT section gate electrode penetrating through the semiconductorpattern, and in the arrangement of FIG. 12(a) with the TFT section gateelectrode not penetrating through the semiconductor pattern.

As can been seen with the explanation above, it is necessary in the TFTsection that the front end of the TFT section gate electrode 66 extends(juts out) beyond the periphery of the a-Si layer 68.

Next, the following will explain the case where a positive potential isapplied to the gate electrode 13. When a gate electrode 13 is suppliedwith a positive potential, the electrons in the n+ layer 69 areattracted to the potential of the TFT section gate electrode 66, andtherefore carriers exist in the channel section. Therefore, a currentcan easily flow between the source and drain electrodes, and the TFT isturned on. As one example of this case, a voltage of 10V was applied tothe gate electrode. As a result, a current of approximately 1 μA flowsbetween the source and drain electrodes. Here, the voltage appliedbetween the source and drain electrodes was 10V. Since the electronshave a behavior to flow in the shortest route between the source anddrain electrodes when the TFT is ON, the TFT section gate electrode 66is not required to penetrate through the semiconductor pattern.

However, there arises a problem when the a-Si layer 68 is not balancedwith respect to the TFT section gate electrode 66, as shown in FIG. 13.Particularly, in the state shown in FIG. 13, the drain electrode 18overlaps with the a-Si layer 68 only in a portion in the widthdirection. In this case, the flow of electrons are not sufficientlyobtained in the source electrode 17, and therefore, the ON currentincreases or decreases in proportion to the width of the portion of thedrain electrode 18 which overlaps with the a-Si layer 68. When having aplurality of such TFTs, the liquid crystal panel has variation ofcharging condition of each pixel, thus causing unevenness of the image.For this reason, the source electrode 17 and the drain electrode 18 areboth required to overlap with the a-Si layer 68, by their whole widths.

In this view, in the step for providing the resist layer 67 to be usedfor processing the a-Si layer 68, by dropping the resist material fromthe inkjet head 33 of a pattern forming equipment, shooting error(dropping error in the dropping to a target dropping position), i.e.,dropping accuracy needs to be taken into account so as to realize suchan arrangement that the a-Si layer 68 entirely overlaps with the sourceelectrode 17 and the drain electrode 18 in the channel section 72 andthe front end portion of the TFT section gate electrode 66 is extendingout of the a-Si layer 68.

Further, in order to create such an arrangement, the shooting error(dropping accuracy) upon dropping of the resist material from the inkjethead 33 of a pattern forming equipment, or more specifically, thedropping accuracy (±10 μm, for example) of a pattern forming equipmentwith respect to the diameter (30 μm, for example) of the resist layer67, needs to be taken into account so as to provide a sufficient lengthto the TFT section gate electrode 66 so that the front end portionextends out of the a-Si layer 68.

Note that, in the example above, the light blocking film (light blockinglayer) 62 is formed on a lower portion of the TFT section 22 (in a lowerlayer than the semiconductor layer 16); however, the light blocking film62 may be formed on an upper portion of the TFT section 22 (in an upperlayer than the semiconductor layer 16). Here, the following will explainthe case where the light blocking film 62 is formed on an upper portionof the TFT section 22, with reference to FIGS. 14(a) through 14(d). FIG.14(a) is a vertical cross-sectional view showing the TFT array substrate11 after the partial oxidation treatment of the channel section 72 iscompleted, and FIG. 14(b) is a vertical cross-sectional view of the TFTarray substrate 11 showing the step for forming a light blocking film 62on an upper portion, and FIG. 14(c) is a cross-sectional view, takenalong the lines M-M of FIG. 14(d), and FIG. 14(d) is a plan view of theTFT array substrate 11 having the upper light blocking film 62 andshowing a state where forming of a pixel electrode 21 is completed.

As explained in the Gate line pre-processing step 41, the light blockingfilm 62 is optional. For a particular example, a light blocking film 62formed on an upper layer than the channel section 72 can preventdeterioration of the TFT characteristic, which is caused by unwantedlight from the channel section 72. In the following example, the lightblocking film is formed both on a lower portion and an upper portion ofthe TFT section 22. As circumstances demand, the TFT section 22 mayinclude one or both of the upper and lower light blocking films 62.

After the partial oxidation treatment of the channel section 72 iscompleted as shown in FIG. 14(a), an upper light blocking film 62 isformed by dropping a droplet of a light blocking film material with apattern forming equipment, as shown in FIG. 14(b). Thereafter, aphotosensitive acrylic resin layer 20 is formed, and further, the pixelelectrode 21 is formed, as shown in FIG. 14(c).

The material of the upper light blocking film 62 may be a resin mixedwith TiN, as with the lower light blocking film 62 formed under the gateelectrode 13 (TFT section gate electrode 66). Note that, since the lightblocking film 62 is formed on an electrode in this example, it ispreferable that the light blocking film 62 is made of an insulationmaterial, and does not include components causing deterioration ofperformance of the semiconductor layer 16 by diffusing in thesemiconductor layer 16.

Further, the light blocking film 62 may be formed between a protectionlayer (not shown) on the TFT and the photosensitive acrylic resin layer20. This structure provides such an advantage that, since an inter-layerinsulation layer is provided between the source and drain electrodes 17and 18, and the light blocking film 62, the material of the lightblocking film 62 is not required to be an insulator, or not required tobe decided in consideration of the diffusion of the components in thesemiconductor layer, thus widening the choice of materials. Further, inthis case, since the photosensitive acrylic resin layer 20, which isused for forming the pixel electrode 21 (ITO electrode), is formed afterthe light blocking film 62, the level difference which occurs uponforming of the light blocking film 62 can be flattened by providing thephotosensitive acrylic resin layer 20 thereon. Therefore, the thicknessof the liquid crystal layer becomes even, and prevents occurrence ofunevenness of the display. Further, the light blocking film 62 may beformed before applying ITO to form the pixel electrode 21, i.e., it maybe formed between the photosensitive acrylic resin layer 20 and thepixel electrode 21.

As described, compared to a conventional manufacturing method without aninkjet type pattern forming equipment, the manufacturing method of a TFTarray substrate 11 according to the present invention can reduce thenumber of masks from 5 to 3, thus reducing photolithography processesand number of vacuum deposition devices. On this account, equipmentoutlay can also be greatly reduced.

Second Embodiment

Another Embodiment of the present invention is described below withreference to FIGS. 15 through 21.

A liquid crystal display device according to the present Embodimentincludes a pixel shown in FIG. 15(a). Note that, FIG. 15(a) is a planview showing a schematic configuration of a pixel of a TFT arraysubstrate. Further, FIG. 15(b) is a cross-sectional view, taken alongthe line I-I of FIG. 15(a).

In the TFT array substrate 11 shown in FIGS. 1(a) and 1(b), thepassivation film 19 is formed after the source and drain electrodes 17and 18, and thereafter, a guide for the pixel electrode is formed by thephotosensitive acrylic resin layer 20.

In manufacturing of a TFT array substrate 81 to be used for a liquidcrystal display device according to the present Embodiment, the sourceelectrode 17 and a drain/pixel electrode 82 are formed on the same layerin either of a guide forming process or hydrophilic/hydrophobic processusing a photocatalyst, which are carried out as one manufacturing step.Note that, in the TFT array substrate 81, the drain electrode and thepixel electrode are made of one continuous electrode, and thereforereferred to as a drain/pixel electrode 82. Further, the passivation film83 is formed substantially only on the TFT section 22.

Due to such differences in structure and manufacturing method, the TFTarray substrate 11, on one hand, requires a mask in the manufacturing toform the photosensitive acrylic resin layer 20; and the TFT arraysubstrate 81, on the other hand, does not require in the same step, thusrequiring a less number of masks. However, in the manufacturing of theTFT array substrate 81, a guide for the pixel electrode (drain/pixelelectrode 82) or the hydrophilic/hydrophobic area is formed in the samestep for forming a guide for the source electrode 17. Thus, the TFTarray substrate 81 has a smaller aperture ratio than that of the TFTarray substrate 11.

Further, in the TFT array substrate 11, the pixel electrode 21 and anstorage capacitor electrode 14 are formed as separate layers. Therefore,the drain electrode 18 extends to the storage capacitor section 23, andthe contact hole 24 is formed above the storage capacitor section 23 soas to conduct the drain electrode 18 to the pixel electrode 21. On theother hand, in the TFT array substrate 81, the drain/pixel electrode 82is provided also as an electrode extending to the storage capacitorsection 23.

In both the TFT array substrates 11 and 81, in order to prevent thematerials of the source electrode and the pixel electrode from splashingto the channel section 72, the source and drain electrodes are formed bydropping the electrode material from the inkjet head 33 to a portionaway from the channel section 72. Also, the area for the source anddrain electrodes is formed in a taper shape becoming wider toward thechannel section 72 so that the electrode material flows toward thechannel section 72. An example of this shape is plainly shown in thevicinity of the channel in the drain electrode 18 and the sourceelectrode in FIG. 1(a).

Further, the a-Si layer 68 may be formed by processing the a-Si forminglayer 64 by using a mask, i.e., by using the resist layer 67 formed by asingle (one shot) droplet; however, for a structure including a long TFTextending in parallel to the source electrode 17, the resist layer 67may be formed by two or more droplets (two or more shots) of thematerial.

Next, the following will explain a manufacturing method of the TFT arraysubstrate 81 including a TFT, used for a liquid crystal display deviceaccording to the present embodiment.

In the present Embodiment, the TFT array substrate 81 is manufacturedthrough, as shown in FIG. 16, a gate line pre-processing step 41, a gateline applying/forming step 42, a gate insulation layer/semiconductorlayer depositing step 43, a semiconductor layer forming step 44, asource and drain/pixel electrodes pre-processing step 91, a source lineapplying/forming step 92, a drain/pixel electrode applying/forming step93, a channel section processing step 94, a passivation film formingstep 95. The gate line pre-processing step 41 through the semiconductorlayer forming step 44 are the same as those in manufacturing of the TFTarray substrate 11, and therefore explanations thereof will be omittedhere.

[Source and Drain/Pixel Electrodes Pre-Processing Step 91]

FIG. 17 shows the source and drain/pixel electrodes pre-processing step91. FIG. 17 is a plan view showing the glass substrate 12 after thesemiconductor layer forming step, i.e., the glass substrate 12 providedwith a wiring guide 84 for forming the source electrode 17 and a wiringguide 85 for forming the drain/pixel electrodes 82.

In this step, the wiring guide 84 is formed on an area for forming thesource electrode 17 (source forming area 86), and the wiring guide 85 isformed in an area for forming the drain/pixel electrodes 82 (drain/pixelelectrodes forming area 87). In this Embodiment, the wiring guides 84and 85 were formed by a photoresist material. More specifically, theglass substrate 12 after the semiconductor layer forming step 44 wascoated with a photoresist, and was subjected to pre-baking, and thendeveloped by exposure using a photo mask, and further subjected topost-baking. Each of the wiring guides 84 and 85 thus created had awidth=10 μm, and the width of the groove (the width of the wiringforming area) created with the wiring guide 84 was approximately 15 μm.Note that, the interval between the source and drain electrodes, i.e.,the channel section 72 was set to 4 μm.

Note that, here, the glass substrate 12 may be arranged such that theSiNx surface (the upper surface of the gate insulation layer 15) isprocessed to be provided with hydrophilicity by using an oxygen plasma,and the wiring guides 84 and 85 are processed to be provided withwater-repellence by supplying CF₄ plasma, so that the wiring materialfrom a pattern forming equipment can be smoothly applied to the basesurface.

Further, instead of forming the wiring guides 84 and 85, the glasssubstrate 12 may be subjected to the hydrophilic/hydrophobic processingusing a photocatalyst according to the pattern of wiring electrode, aswith the foregoing gate electrode forming step. Note that, in this case,a particular care is required to prevent the material of the sourceelectrode from being splashing to the pixel electrode.

[Source Line Applying/Forming Step 92]

FIGS. 18(a) and 18(b) show the source line applying/forming step 92.FIG. 18(a) is a plan view showing the source electrode 17 which has beenformed along the wiring guide 84. FIG. 18(b) is a cross-sectional view,taken along the line J-J of FIG. 18(a).

As shown in FIGS. 18(a) and 18(b), in this source line applying/formingstep 92, the source electrode 17 was formed by coating the sourceforming area 86, which is formed by the wiring guide 84, with a wiringmaterial by using a pattern forming equipment. Here, the dischargingamount of the wiring material from the inkjet head 33 was set to 2 pl.Further, Ag particles are used as the wiring material, and the thicknessof the electrode was adjusted to 0.3 μm. Further, baking temperature was200° C., and after the baking, the wiring guide 84 was removed by anorganic solvent.

Note that, in this step, the same wiring material may be used as the oneused for the gate electrode 13; however, the baking temperature isrequired to be at or lower than 300° C., since the a-Si is formed ataround 300° C.

[Drain/Pixel Electrode Applying/Forming Step 93]

FIG. 19(a) and 19(b) show the drain/pixel electrode applying/formingstep 93. FIG. 19(a) is a plan view showing the drain/pixel electrode 82which has been formed along the wiring guide 85. FIG. 19(b) is across-sectional view, taken along the line K-K of FIG. 19(a).

In this drain/pixel electrode applying/forming step 93, the drain/pixelelectrode 82 was formed by applying an ITO particle material to thewiring guide 85 by using a pattern forming equipment, and then was bakedwith a baking temperature of 200° C.

In this manner, only a single mask is required for the source/drainelectrodes forming step and the ITO processing step, unlike theconventional method which uses respective masks for these steps.Further, the use of an inkjet type pattern forming equipment allowsseparate application of the electrode material and the pixel electrodematerial with respect to each pattern by using separate inkjet heads 33.Accordingly, the present method requires a simpler device system andimproves efficiency of material use, thus realizing cost reduction.

[Channel Section Processing Step 94]

This step is carried out for processing the channel section 72 of theTFT. FIGS. 20(a) and 20(b) are cross-sectional views corresponding to aportion taken along the line K-K of FIG. 19(a). Firstly, as shown inFIG. 20(a), the wiring guides 84 and 85 of the channel section 72 wereremoved by an organic solvent or by ashing. Next, as shown in FIG.20(b), the n+ layer 69 was subjected to oxidation treatment by ashing orby using a laser so as to be a nonconductor.

[Passivation Film Forming Step 95]

FIG. 21 shows the passivation film forming step 95. FIG. 19(a) is across-sectional view corresponding to a portion taken along the line K-Kof FIG. 19(a). In this step, a passivation film 83 was formed by apattern forming equipment on a glass substrate 12 which had beenprovided with the source electrode 17 and the drain/pixel electrode 82.

To create the passivation film 83, a transparent inorganic material suchas an ethoxy silane material is applied on the TFT section 22, and thenwas baked with a temperature of approximately 150° C. The material ofthe passivation film 83 may also be a resist material or aphotosensitive resin. Further, the light blocking film 62 may be used asthe material which blocks external light and also operates as blackmatrix on a color filter. Namely, both a transparent material and anopaque material may be used as the material of the passivation film 83.Here, a TFT array substrate 81 is completed.

In comparison with the conventional manufacturing without an inkjetmethod, the number of masks may be reduced from 5 to 2 in themanufacturing steps of the present embodiment, and the source electrode17 and the drain/pixel electrode 82 can be formed by one guide formingstep. Therefore, the number of masks can further be reduced less thanthat of the manufacturing of the TFT array substrate 11.

Further, as with the manufacturing of the TFT array substrate 11, numberof vacuum deposition equipments can be reduced.

Note that, the foregoing example uses a-Si for the semiconductor layer;however, an organic semiconductor or a particle type semiconductormaterial may also be used. In this case, a step for directly applying asemiconductor material from a pattern forming equipment is carried outinstead of the processing step of a-Si of the TFT array substrate.Accordingly, application of a resist or resin material, dry etching, andremoval process of the resist or resin material can be omitted, therebyfurther simplifying the manufacturing.

FIGS. 22(a) through 22(c) show a manufacturing method of thesemiconductor layer 16 according to the foregoing manner.

In this manner, after forming the gate insulation layer 15, asemiconductor material is directly dropped from a pattern formingequipment onto the gate insulation layer 15 in the TFT section 22, andthe material is then baked to create the semiconductor layer 16, asshown in FIGS. 22(b) and 22(c). In this example, an organicsemiconductor material such as polyvinyl carbazole (PVK) orpolyphenylene vinylene (PPV) may be used as the semiconductor material.

In contrast to an a-Si formed by a CVD, etching process is not necessaryto the foregoing materials since they can be formed to be thesemiconductor layer 16 with a droplet (1 shot) from a pattern formingequipment. Thus, hydrophilic/hydrophobic processing is not necessary inthe area for forming the semiconductor layer 16, in this case.

The TFT array substrates 11 and 18 described in Embodiments 1 and 2 wasarranged so that the gate electrode 13 includes the TFT section gateelectrode 66, which is branched out from the main line of the gateelectrode 13; and the TFT was formed on this TFT section gate electrode66. In this example, the gate electrode 13 does not include a branchelectrode (TFT section gate electrode 66).

As shown in FIG. 23, the semiconductor layer 16 is formed on the gateelectrode 13 (gate line), and a branch electrode 17 a from the sourceelectrode 17 extends to the channel section 72 (TFT section 72).Meanwhile, the drain electrode 18 linearly extends from the storagecapacitor section 23 constituting the storage capacitor, and reaches tothe channel section 72. Note that, this example has been explained as anarrangement compatible with the First Embodiment shown in FIG. 1;however, this example may also be adopted for the Second Embodimentshown in FIG. 15.

In the TFT array substrate 11 of this example, since the gate electrode13 does not include a branch electrode, the foregoing arrangement with abranch electrode (TFT section gate electrode 66) penetrating through thesemiconductor pattern is not necessary.

This arrangement of the TFT array substrate 11 is effective for aconfiguration where the gate electrode 13 has relatively narrow width,for example in a range between 10 μm and 20 μm. In a display panel of ator less than a range of 10-15 inches in diagonal screen measurement, thegate electrode 13 is formed with a relatively narrow width and shortlength. On the other hand, in a display panel of at or larger than 20inches, the width of the gate electrode 13 becomes wider for reducingthe resistance. If the present example is adopted in this case, thewidth of the gate electrode in the TFT forming area needs to be narrow.Namely, the present arrangement is effective in a case where the lengthof the TFT is substantially same as the width of the gate electrode.

Note that, since there also are influences of the resistance ofmaterials and other design parameters, the foregoing relation betweenthe size of the screen and the width of the gate electrode is not alwaystrue.

Further, in the foregoing explanation, the shape of the droplet refersto a state of a droplet when dropped from a pattern forming equipment.The contour of this shape has a curvature. Therefore, if only onedroplet is dropped, or plural droplets are dropped onto the sameposition, the shape of the droplet becomes a circular or a substantiallycircular shape, as shown in FIG. 24.

Further, the shape of the droplet is not always a circular or asubstantially circular shape but can be a deformed circular shape (acollapsed or distorted circle). For example, the shape may be asubstantially circular shape deformed from a circle, as shown in FIG.25(a), a shape having a concave portion, as shown in FIG. 25(b), a shapepartly including a convex portion, as shown in FIG. 25(c). It is assumedthat such a shape with a contour having a curvature is created due todelicate difference of surface condition of the substrate on which thedroplet is dropped, or due to air resistance when the droplet splashes.The foregoing shapes all satisfy the regulation of the present inventionfor the shape of droplet, because they each are regarded immediateshapes created by dropping.

Further, the shape of droplet is not necessarily created by a singledroplet but by plural droplets. FIG. 26(a) shows a case where a deformedoval shape is formed by two droplets. The respective droplets merge as aresult of dropping, or merge into a contour after dropping, and resultin a shape with a contour having a curvature. FIG. 26(b) shows anexample formed by three droplets.

It should be noted that the present example do not intend the stateshown in FIG. 27(a) where a plural of infinitesimal droplets areapplied, which results in the shape shown in FIG. 27(b).

As stated above with reference to FIGS. 1(a) and 15(a), the liquidcrystal display device according to the present invention has a TFTsection 22 with the TFT section gate electrode 66 of the gate electrode13 penetrating through the semiconductor pattern (semiconductor layer16) having substantially a circular shape, so as to prevent a leakcurrent flowing between the source and drain electrodes when the gate isOFF.

More specifically, the characteristic of the TFT section 22 of theliquid crystal display device of the present invention can be expressedas the relation between the drain current (Id) and the gate voltage (Vg)shown in FIG. 29. Note that, the graph in FIG. 29 uses a TFT (shown inFIG. 30) as a comparative example, with the TFT section gate electrode66 of the gate electrode 13 not penetrating through the semiconductorlayer 16 due to shooting error of the droplet upon forming of thesemiconductor layer.

As can be seen in FIG. 29, when the gate voltage has a negative value,i.e., the gate is OFF, the drain current seldom flows in the TFT of thepresent invention; in contrast, the drain current slightly flows in theTFT shown in FIG. 30. Specifically, when the gate is OFF, the draincurrent (leak current) seldom flows in the TFT of the present inventionbut slightly flows in the TFT shown in FIG. 30.

Note that, the direction for the TFT section gate electrode 66 topenetrate through the semiconductor layer 16 is not limited. Forexample, the TFT section gate electrode 66 may penetrate along thesource electrode 17, as shown in FIG. 31, or may penetrate along thedrain electrode 18, as shown in FIG. 32.

In the foregoing arrangement with the TFT section gate electrode 66penetrating through the semiconductor layer 16 so as to prevent a leakcurrent between the source and drain electrodes when the gate is OFF,the larger quantity of penetration is preferable when considering ashooting error, because it makes it easier to appropriately shoot adroplet upon forming of the semiconductor layer 16, so that a leakcurrent can be prevented. However, when adopting the TFT for a liquidcrystal display device, particularly in a transmissive liquid crystaldisplay device, there arises a problem of a decrease of aperture ratio.Note that, the decrease of aperture ratio does not occur in case of areflective liquid crystal display device.

In view of this problem, the following will explain an Embodiment as anexample of fabrication of a semiconductor layer, in which a droplet isapplied in a certain position, so as to create a semiconductor layer notcausing a leak current while also preventing a decrease of apertureratio.

Third Embodiment

Still another Embodiment of the present invention is described belowwith reference to FIGS. 33 through 36.

A liquid crystal display device according to the present Embodimentincludes a pixel shown in FIG. 33. FIG. 30 is a plan view showing aschematic configuration of a pixel of a TFT array substrate. Further,this pixel is the same as that shown in FIG. 1(a), which is used for atransmissive liquid crystal display device. For ease of explanation,materials having the equivalent functions as those shown in the drawingspertaining to FIG. 1(a) will be given the same reference symbols, andexplanation thereof will be omitted here.

As shown in FIG. 33, a TFT array substrate 201 according to the presentEmbodiment has substantially the same configuration as that of the TFTarray substrate 11 shown in FIG. 1(a) except for a protrusion electrode202 extending from an end of the TFT section gate electrode 66, and isprovided in contact with the source electrode 17.

The protrusion electrode 202 has a narrower width than that of the TFTsection gate electrode 66 and provided in contact with the sourceelectrode 17.

With this configuration, the aperture ratio of the TFT array substrate201 does not decrease even in the case where the semiconductor layer 16has the configuration to prevent a leak current between the source anddrain electrodes when the gate is OFF.

Further, FIG. 34 shows a TFT array substrate 211 as another possibleexample, in which a protrusion electrode 212 extending from an end ofthe TFT section gate electrode 66 is provided in contact with the drainelectrode 18.

As with the case above, this configuration does not cause the decreaseof aperture ratio of the TFT array substrate 211 even in the case wherethe semiconductor layer 16 has the configuration to prevent a leakcurrent between the source and drain electrodes when the gate is OFF.

Here, the following will minutely explain a configuration in thevicinity of the TFT section 22 with reference to FIGS. 35 and 36.

FIG. 35 is a magnified view in the vicinity of the TFT section 22 of theTFT array substrate 201 shown in FIG. 33, in which the protrusionelectrode 202 extends along the source electrode 17. Further, FIG. 36 isa magnified view in the vicinity of the TFT section 22 of the TFT arraysubstrate 211 shown in FIG. 34, in which the protrusion electrode 212extends along the drain electrode 18.

As shown in FIG. 35, a protrusion electrode 202 extends from an endportion 66 a of the TFT section gate electrode 66, and the width of theprotrude electrode 202 is set narrower than that of the end portion 66a.

Note that, in the present Embodiment, the width of the end portion 66 aof the TFT section gate electrode 66 is set to 10 μm, the width of theprotrusion electrode 202 is set to 5 μm, the distance between the sourceand drain electrodes 17 and 18, i.e., the channel length of TFT CH isset to 5 μm.

Further, the TFT section gate electrode 66 generally has a wider widththan that of the TFT length CH, and is provided with a portion OV(overlapping portion) where the source electrode 17 and the drainelectrode 18 are overlapped with each other. Therefore, as with thepresent Embodiment, the channel length of TFT CH of 5 μm requires thewidth of the TFT section gate electrode 66 to be approximately 10 μm.

Note that, the value specified here is only an example, and presentinvention is not limited to this value.

Further, an end portion of the protrusion electrode 202 has to be out ofthe semiconductor layer 16 (a-Si layer); however, the width of the endportion of the protrusion electrode 202 is not restricted by the TFTlength CH.

More specifically, the end portion of the protrusion electrode 202extends out of the semiconductor layer 16 so that a leak current doesnot flow from the source electrode 17 to the drain electrode 18 when theTFT section gate electrode 66 becomes OFF state by being supplied with avoltage. Therefore, the end portion of the protrusion electrode 202 isnot required to have the same width as that of the end portion 66 a ofthe TFT section gate electrode 66.

Accordingly, since the end portion of the protrusion electrode 202 maybe provided with a narrower width than that of the end portion 66 a ofthe TFT section gate electrode 66, the protrusion electrode 202 can bedisposed closely along the source electrode 17, as shown in FIGS. 33 and35, thereby preventing the decrease of aperture ratio of the TFT arraysubstrate 201.

However, it should be noted that, it is preferable that the protrusionelectrode 202 is not overlapped with the source electrode 17. If theprotrusion electrode 202 and the source electrode 17 are overlapped witheach other, a new capacitance is generated between the protrusionelectrode 202 and the source electrode 17 via the gate insulation layer(not shown), and causes delay or blunt waveform of the signal flowing inthe source electrode 17.

Here, the semiconductor layer 16 shown in FIG. 35 is formed by a dropletwhich has been applied on a portion upper in the figure than the targetposition (the center of the source and drain electrodes).

Incidentally, when the border line (outline of the circular arc) of thesemiconductor layer 16 is shifted upper than an end face 17 a of thesource electrode 17, the effective width of the TFT becomes narrower.Accordingly, when the semiconductor layer 16 is formed with an upperborder line than that in FIG. 35, the characteristic of the TFTdecreases.

Thus, the border line of the semiconductor layer 16 is preferably lowerthan the end face 17 a of the source electrode 17.

Meanwhile, the upper end of the semiconductor layer 16 (the border areanear the end portion 66 a of the TFT section gate electrode 66) extendsfar beyond the end portion 66 a of the TFT section gate electrode 66,and disposed above the figure. Here, if the protrusion electrode 202 isnot provided on the end portion 66 a of the TFT section gate electrode66, the semiconductor layer 16 extending beyond the end portion 66 a ofthe TFT section gate electrode 66 causes a leak current between thesource and drain electrodes. More specifically, there arises a decreaseof the characteristic of the TFT section 22.

In such a case, the end portion 66 a of the TFT section gate electrode66 is required to be further extended; however, when the end portion 66a extends upward in the figure with the same width, it invades the pixelarea of the TFT array substrate 201.

In this view, as shown in FIG. 35, the protrusion electrode 202 isextended along the source electrode 17 with a narrower width than thatof the end portion 66 a of the TFT section gate electrode 66, thuspreventing the decrease of the aperture ratio of the pixel section inthe TFT section gate electrode 66.

Further, in the example of FIG. 35, the upper end of the protrusionelectrode 202 is far beyond the border area of the semiconductor layer16, and therefore a leak current does not occur. In this way, it ispossible to prevent the decrease of the characteristic of the TFTsection 22. Besides, the characteristic of the TFT section can furtherbe improved.

Further, as with the protrusion electrode 212 shown in FIG. 36, it maybe formed by extending from the end portion 66 a of the TFT section gateelectrode 66 along the drain electrode 18. The protrusion electrode 212is extended not upward in the figure, i.e., along the source electrode17 but along the drain electrode 18. As with the protrusion electrode202, the width of the protrusion electrode 212 is narrower than that ofthe end portion 66 a of the TFT section gate electrode 66.

FIG. 36 shows the semiconductor layer 16 shifted to the right of thefigure. In this example, the end face 17 a of the source electrode 17comes right on the border of the semiconductor layer 16, and thereforethe semiconductor layer 16 is no longer allowed to be shifted upward orto the right of the figure. Here, the upper end portion of theprotrusion electrode 212 needs to be out of the semiconductor layer 16.

Since the protrusion electrode 212 extends along the drain electrode 18,it is possible to prevent the decrease of the aperture ratio of thepixel section in the TFT array substrate 211. However, the protrusionelectrode 212 should not be overlapped with the drain electrode 18 so asto prevent generation of the capacitance which draws a charge to thepixel section and causes undercharge.

Note that, it is preferable for both the protrusion electrode 202 andthe protrusion electrode 212 not to be overlapped with the sourceelectrode 17 or the drain electrode 18; however, when the overlappingoccurs, the charging of the pixel section can be adjusted inconsideration of the capacitance, by controlling a signal flowing toeach electrode.

The present Embodiment has explained an example of providing theprotrusion electrode 202 along the source electrode 17 as shown in FIG.33, and an example of providing the protrusion electrode 212 along thedrain electrode 18 as shown in FIG. 34. Such configuration can prevent aleak current between the source electrode 17 and the drain electrode 18when the TFT section gate electrode 66 in the TFT section 22 becomes OFFstate by being supplied with a voltage, while preventing the decrease ofthe aperture ratio of the pixel section in the TFT array substrate.

In other words, the Third Embodiment has explained the formingdirections of the protrusion electrode 202 and the protrusion electrode212 which extend from the end portion 66 a of the TFT section gateelectrode 66.

The following Fourth Embodiment describes the extent to which the endportion 66 a of the TFT section gate electrode 66 protrudes from thesemiconductor layer 16.

Fourth Embodiment

Yet another Embodiment of the present invention is described below withreference to FIGS. 37 and 38.

The present Embodiment explains an example of forming a TFT by an inkjetmethod while taking account of shooting error of a droplet.

Firstly, the following will discuss the shooting error of a droplet. Theshooting error occurs depending on where the droplet lands in and howthe droplet spreads. Here, the shooting error is discussed in view oftwo factors. The first is the occupied area of the droplet afterdischarged, which depends on the amount of liquid and the way itspreads. The second is dropping off the target position.

Depending on unevenness of discharge amount of the droplet, or surfacecondition of the substrate (hydrophilic or hydrophobic), the firstfactor may include unpredictability of the shape of the droplet area.

Here, the unpredictability of the shape of the droplet area refers tovariation of the outline of the applied droplet. This variation resultsfrom unevenness of the spread of liquid due to difference in dropcondition. The unpredictability occurs even when the discharge isperformed with a predetermined amount of liquid in order to create a anapplication area of desirable size which takes account of thewettability of the substrate, which depends on the processing of thedischarging surface and droplet material.

The second factor includes such as mechanical error, i.e., positioningaccuracy of the stage, inkjet head nozzle processing error, variation ofdimension or shape of multi-nozzles, the difference of distance betweensubstrate and nozzles, error caused by thermal expansion of the inkjethead. Further, it also relates to variation of ink discharging directionwhich is caused by deposits in the nozzle which changing wettingcondition of the nozzle surface with ink.

The dropping accuracy of the inkjet also relates to many othercomplicated factors; however, the present Embodiment will be explainedbased on the foregoing two factors.

In the TFT shown in FIG. 37, the target dropping position is the centerof the channel section 72. The range of dropping error is denoted by acircle 301 whose radius=Δ2, which is equal to the distance from thetarget position. Here, Δ2 denotes an error due to dropping off thetarget position (stage error+mechanical processing error+dropping angleerror+thermal expansion+ . . . ). More specifically, the center of thedroplet after the dropping will be within the circle having the radiusR=Δ2, as shown in FIG. 37, where Δ2 denotes the error of dropping offthe target dropping position, which is caused by the mechanical error orcondition of the nozzle (the second error taking account of dropping offthe target position).

Further, the minimum range of area required to be covered by the a-Siarea (semiconductor layer 16), which is processed by a resist (droplet)applied from an inkjet method, is shown by the width W and the length Lin the channel section of the TFT. Accordingly, assuming that thedroplet discharged from the inkjet forms a circle, the circle (thecircle 302 in the figure) has the radius r from the center f of thechannel section. Here, the radius r denotes the distance from the centerof the TFT (the center f of the channel section) to the end of thechannel section. In other words, the radius r denotes the distance fromthe center of the channel section to the outermost end of the channelsection.

The circle 303 in the same figure has a larger radius R=r+Δ1 by takingaccount of error caused by variation of liquid amount and variation ofthe way the droplet spreads, i.e., taking account of an error of theradius depending on the amount of liquid, and unpredictability of thespread shape of the liquid. Here, Δ1 denotes an error taking account ofvariation of liquid amount+variation of the spread (error of thespread). More specifically, Δ1 denotes the first error taking account ofvariation of discharging amount of the droplet and variation of thespread of the droplet after the discharge, upon forming of thesemiconductor layer.

Accordingly, when the droplet is dropped into the center of the channelsection, the channel section can be covered if the discharging amount ofthe droplet is adjusted to form the circle 303 having the radius=r+Δ1taking account of unpredictability of the amount of the liquid and thearea of the droplet.

Further, also considering the dropping position error Δ2, the circle 304with a radius=r+Δ1+Δ2 denotes a required radius for covering the channelsection, when the discharge is carried out with respect to the center fof the channel section.

Accordingly, the semiconductor layer 6 after processing preferably hasthe radius R given by the following formula (3).R>r+Δ1+Δ2  (3)

In FIG. 37, the border of the semiconductor layer 6 is denoted by thedistance L1 which extends from the upper ends of the source and drainelectrodes 17 and 18 (the end portion near the end portion 66 a of theTFT section gate electrode 66).

Thus, when the semiconductor layer 6 is processed by discharging adroplet of resist with respect to the center of the TFT channel section,the distance L1 extending from the upper ends of the source and drainelectrodes 17 and 18 preferably satisfies the following formula (4).L1>Δ1+Δ2  (4)

Note that, the width W of the channel section of the TFT section 22 islonger than the length L in this case, and therefore the length L isextremely short. Thus, this example applies the condition of W/2≈r.

Since the circle 304 with the radius R≈r+Δ1+Δ2 extends toward the endportion 66 a by the error Δ2 from the target dropping position, the endportion 66 a, which is the open end portion of the TFT section gateelectrode 66, is preferably provided according to the following formula(1),L3>r+Δ1+2Δ2  (1)

where L3 expresses the distance from the center f of the channel sectionto the end portion 66 a.

Further, the distance L2 from the end portions of the source and drainelectrodes 17 and 18 to the end portion 66 a preferably satisfies thefollowing formula (2), where w/2≈r.L2>Δ1+2Δ2  (2)

In this figure, Δ2 is multiplied by 2 taking account of both plusdirection and minus direction of the error.

Note that, the condition for determining the position of the end portion66 a of the TFT section gate electrode 66 may be given by either of theforegoing formulas (1) and (2).

FIG. 38 shows the end portion 66 a of the TFT section gate electrode 66bending to the right of the figure. In this case, the position of theend portion 66 a of the TFT section gate electrode 66 cannot berestricted by the distance from the end portions of the source and drainelectrodes 17 and 18; thus, the position is restricted by the distancefrom the center f of the channel section. In this case, the position offront end of the end portion 66 a of the TFT section gate electrode 66is preferably determined with the condition given by the formula (1), asshown in FIG. 38.

Here, the length of the channel section of the TFT section 22 of theliquid crystal panel is set as W=25 μm, L=5 μm, for example. The radiusr in this length is 12.7 μm and the dropping position error Δ2 of theinkjet is 15 μm. Further, the error Δ1 due to unpredictability of theliquid amount and the outline border is 5 μm.

Accordingly, in this case, the semiconductor layer 6 after processing atleast requires an area created by a circle with a radius 12.7+5+15=32.7μm.

Further, when the end portion 66 a of the TFT section gate electrode 66extends straight upward as shown in FIG. 37, the position of the endportion 66 a is preferably determined by setting the distanceL2>5+2×15=35 μm from the end portions of the source and drain electrodes17 and 18. Further, the end portion 66 a is preferably provided with thedistance given by L3>12.7+5+2×15=47.7 μm from the center f of thechannel section. Note that, this example applies the condition ofw/2=12.5 μm≈r=12.7 μm.

The TFT array substrate according to the Third and Fourth Embodiments ismanufactured by performing the following manufacturing step in additionto the manufacturing steps shown in the First and Second Embodiments.

Specifically, in the step for forming the gate electrode, which isdescribed in the foregoing First and Second Embodiments, the TFT sectiongate electrode 66 (a branch electrode from the gate electrode 13) isformed with such an arrangement that the portion (the end portion 66 a)protruded from the semiconductor layer 16 is smaller in width than theportion in the area of the semiconductor layer 16. With thisarrangement, the TFT array substrate of the Third Embodiment can becreated.

Further, in the step for forming the gate electrode, which is describedin the foregoing First and Second Embodiments, the TFT section gateelectrode 66 (a branch electrode from the gate electrode 13) is formedwith such an arrangement that the portion (the end portion 66 a)protruded from the semiconductor layer 16 is formed along one of thesource electrode 17 or the drain electrode 18. With this arrangement,the TFT array substrate of the Third Embodiment can be created.

Further, in the step for forming the gate electrode, which is describedin the foregoing First and Second Embodiments, the TFT section gateelectrode 66 (a branch electrode from the gate electrode 13) is formedwith the condition given by the following formula (1),L3>r+Δ1+2Δ2  (1)

where r denotes the distance from the center of the channel section tothe outermost end of the channel section, Δ1 denotes the first errortaking account of variation of amount of the droplet for constitutingthe semiconductor layer 16 and variation of the spread of the droplet,Δ2 denotes the second error considering the error caused by dropping ofthe droplet off the target position, and L3 denotes the distance fromthe center of the channel section to the open end of the branchelectrode. With this arrangement, the TFT array substrate of the FourthEmbodiment can be created.

Further, in the step for forming the gate electrode, which is describedin the foregoing First and Second Embodiments, the TFT section gateelectrode 66 (a branch electrode from the gate electrode 13) is formedwith the condition given by the following formula (2),L2>Δ1+2Δ2  (2)

where Δ1 denotes the first error taking account of variation of theamount of the droplet for constituting the semiconductor layer 16 andvariation of the spread of the droplet, Δ2 denotes the second errorconsidering the error caused by dropping of the droplet off the targetposition, and L2 denotes the distance from the end portions (the endportions near the end portion 66 a of the TFT section gate electrode 66)of the source and drain electrodes of the TFT section 22 to the open endportion of the TFT section gate electrode 66. With this arrangement, theTFT array substrate of the Fourth Embodiment can be created.

Further, in the step for dropping a droplet of a resist material on thesemiconductor layer 16 so as to create the resist layer with the form ofthe dropped droplet, which is described in the foregoing First andSecond Embodiments, the resist layer is formed with the condition givenby the following formula (3),R>r+Δ1+Δ2  (3)

where r denotes the distance from the center f of the channel section tothe outermost end of the channel section, Δ1 denotes the first errortaking account of variation of the amount of the droplet forconstituting the semiconductor layer 16 and variation of the spread ofthe droplet, Δ2 denotes the second error considering the error caused bydropping of the droplet off the target position, and R denotes a radiusof the resist layer, which is set according to the distance from thecenter of the channel section. With this arrangement, the TFT arraysubstrate of the Fourth Embodiment can be created.

Fifth Embodiment

Further embodiment of the present invention is described below withreference to FIGS. 39 through 43.

A liquid crystal display device according to the present embodiment haspixels shown in FIG. 39(a). FIG. 39(a) is a plan view showing theschematic structure of one pixel in a TFT array substrate of the liquidcrystal display device. FIG. 39(b) is a cross-sectional view, takenalong the line M-M of FIG. 39(a). For members (structures) havingsubstantially same functions as those shown in the drawings pertainingto the first embodiment of the present invention will be given the samereference symbols, and explanation thereof will be omitted here.

As illustrated in FIGS. 39(a) and 39(b), a TFT array substrate 121includes a glass substrate 12 whereon gate electrodes 13 and sourceelectrodes 17 are arranged in a matrix manner, and the storage capacitorelectrodes 14 are formed between adjacent gate electrodes 13.

On a gate electrode 13, a semiconductor layer 16 including an a-Si layeris formed in a substantially circular shape via the gate insulatinglayer 15, and on this semiconductor layer 16, a conductor layer 122, asource electrode 17 and a drain electrode 18 are formed.

As illustrated in FIG. 39(b), the conductor layer 122 is formed betweenthe semiconductor layer 16 and the source electrode 17 or the drainelectrode 18 of the TFT section 22. The conductor layer 122 has aportion formed in a droplet shape where the conductor layer 122 and thesemiconductor layer 16 have substantially the same shape.

In the present embodiment, the semiconductor layer 16 is formed throughthe steps of depositing and processing a film by the CVD as in the firstembodiment. The conductor layer 122 is formed by dropping droplets of aconductor material (a material containing metal, for example). As willbe explained later, the semiconductor layer 16 is formed in a shapereflecting the shape of the droplet formed in the process of forming theconductor layer 122, i.e., the shape of a conductor forming layer 123.Thus, the portion having the droplet of the conductor layer 122 hassubstantially the same shape as the semiconductor layer 16. The processof forming the conductor layer 122 will be explained in details later inthe explanations of the manufacturing process.

In the present embodiment, the pattern forming equipment, whichdischarges or drops a material of a layer to be formed, for example, bythe inkjet method, is adopted for manufacturing the TFT array substrate121 as in the first embodiment. Specifically, for example, the patternforming equipment of FIG. 2 adopted in the first embodiment may beadopted.

The following will explain a manufacturing method of the TFT arraysubstrate 121. Here, explanations will be given in the case ofmanufacturing the TFT array substrate 121 adopting the pattern formingequipment of FIG. 2 of the first embodiment. Thus, the manufacturingsteps of the manufacturing method of the present embodiment are similarto the manufacturing steps shown in FIG. 3 as explained in the firstembodiment.

Specifically, as shown in FIG. 40, the manufacturing method of the TFTarray substrate 121 includes: a gate line pre-processing step 41, a gateline applying/forming step 42, a gate insulation layer/semiconductorlayer depositing step 43, a semiconductor layer forming step 141, asource/drain lines pre-processing step 45, a source/drain linesapplying/forming step 142, a channel section processing step 143, apassivation film forming step 48, a passivation film processing step 49,and a pixel electrode forming step 50. In the above steps, the stepsother than the semiconductor layer forming step 141, the source/drainlines applying/forming step 142, and the channel section processing step143 are substantially the same as the corresponding steps in the firstembodiment, and explanations thereof shall be omitted here.

[Semiconductor Layer Forming Step 141]

The semiconductor layer forming step 141 is explained below withreference to FIG. 41(a) to FIG. 41(d). FIG. 41(d) is a plan view showingthe glass substrate 12 after the semiconductor layer forming step 141.FIGS. 41(a) and 41(b) are cross-sectional views corresponding to aportion taken along the line N-N of FIG. 41(d), and FIG. 41(c) is across-sectional view, taken along the line N-N of FIG. 41(d).

FIGS. 41(a) through 41(c) are cross-sectional views respectively showthe state directly before starting the semiconductor layer forming step,the state in the semiconductor layer forming step and the state afterthe semiconductor layer forming step.

FIG. 41(a) is a cross-sectional view showing the state of the glasssubstrate 12 where the gate insulation layer/semiconductor layerdepositing step 43 of FIG. 40 is completed.

In this step, as shown in FIG. 41(b), droplets of a conductor materialis dropped from a pattern forming equipment onto the n+ film forminglayer 65 in a portion right above a TFT section gate electrode (branchelectrode) 66, which is branched out from the main line of the gateelectrode 13. The conductor material thus applied by dropping is thenbaked at 250° C. The resulting conductor forming layer 123 is used as apattern for processing the n+ film-forming layer 65 and the a-Si filmforming layer 64. In this embodiment, the conductor forming layer 123 isformed by a single droplet. The discharging amount of the conductormaterial is set to, for example, a 10 pl droplet. As a result, acircular pattern with a diameter=30 μm is formed on a predeterminedposition above the TFT section gate electrode 66.

In this embodiment, in consideration of the temperature at which thea-Si is formed at around 300° C., the baking temperature is set to 250°C. to be lower than 300° C.

In the present embodiment, for the conductor forming layer 123, Mo isadopted. However, the material for the conductor forming layer is notlimited to Mo, and, other than Mo, for example, W, Ag, Cr, Ta, Ti or analloy material including any of the above elements as a main element, ametal material containing any of the above elements as a main elementand a non-metal element such as N, O, C, etc., or a metal oxide such asITO (Indium Tin Oxide), SnO (Tin Oxide), etc., may be adopted.

For the conductor material for use in forming the conductor forminglayer 123, a material prepared by dispersing in an organic solvent, Mofine particles coated with an organic film is adopted. However, amaterial in a form of a paste, or a material including a metal materialas a metal compound dissolved in an organic solvent may be adopted.Furthermore, by controlling dissociation temperatures of the surfacecoating layer for protecting the fine particles and the organic materialin the solvent according to the required baking temperature, the desiredresistance and the surface condition can be obtained. Incidentally, thedissociation temperatures denote temperatures at which the surfacecoating layer and the solvent evaporate.

For the selection of the material which constitutes the conductorforming layer 123, it is necessary to consider such features as beingtolerable in the following dry etching process, and the selectivity inetching using a pattern of the source electrode and a drain electrode inthe channel section processing step 143. Further, such feature as beingnot diffusible to the semiconductor layer 16 for avoiding adverseeffects on the TFT characteristics later is essential for the materialof the conductor forming layer 123.

Next, as shown in FIG. 41(c), the n+ film forming layer 65 and the a-Sifilm forming layer 64 are subjected to dry etching using a gas (such asSF₆+HCl) so as to form an n+ layer 69 and an a-Si layer 68.

As described, in the semiconductor layer forming step 141, the patternof the conductor forming layer 123 discharged from the pattern formingequipment directly reflects the shape of the semiconductor layer 16which is made up of the n+ layer 69 and the a-Si layer 68. Namely, thesemiconductor layer 16 is formed in a circular pattern or in asubstantially circular pattern made up of a curved line, according tothe shape of the material of the conductor forming layer 123 dropped onthe glass substrate 12 from an inkjet head 33 (FIG. 2).

Though the conductor forming layer 123 of the present embodiment isformed by a single droplet from the inkjet head 33, the conductorforming layer 123 may be formed by plural droplets. However, it shouldbe noted that, when forming the conductor forming layer 123 bydischarging a plurality of extremely small droplets with high precision,a long time is required for forming a semiconductor layer 16, and thelife of the inkjet head 33 is shortened as more dot number is required.Therefore, in the case of forming the conductor forming layer 123 bydropping a plurality of droplets, it is desirable to set a size of layer(film) in consideration of the manufacturing time, the life of theinkjet head, etc.

Further, another noticeable characteristic of the semiconductor layerforming step 141 lies in that a special treatment is not required forthe surface which receives droplets discharged from the inkjet head 33as in the first embodiment.

In the conventional method, a mask, or photolithography process isrequired for the patterning of the semiconductor layer. In contrast,according to the semiconductor layer forming step 141 of the presentinvention, the mask pattern (corresponding to the resist layer 67 inFIG. 5(b)) is directly drawn with a droplet dropped from the inkjet head33, and the mask and the photolithography process can be omitted. As aresult, a significant cost reduction can be realized.

[Source/Drain Lines Applying/Forming Step 142]

FIG. 42(a) is a plan view showing the state of the glass substrate 12having gone through the source/drain line pre-processing step 45.

This source/drain lines applying/forming step 142 is shown in FIG. 42(b)and FIG. 42(c). FIG. 42(b) is a plan view showing the source and drainelectrodes 17 and 18 which are formed along the wiring guide 71, andFIG. 42(c) is a cross-sectional view, taken along the line O-O of FIG.42(b).

The Source/drain lines applying/forming step 142 of the presentembodiment is performed in the same manner as the first embodiment.However, for the selection of the wiring material, durability accordingto the etching process conditions for the conductor forming film 123 tobe described later need to be considered. In the present embodiment, forthe wiring material, a material prepared by dispersing Al, fineparticles coated with an organic film in an organic solvent is adopted.However, the wiring material of the present invention is not limited tothis material. Other than Al, an Al alloy such as Al—Ti, Al—Nd, etc.,Ag, or such Ag alloy as Ag—Pd, Ag—Cu, etc., ITO (Indium Tin Oxide), Cu,Cu—Ni, etc. These materials may be individually adopted, or in a form ofparticles of an alloy material, or in a form of a paste dissolved in anorganic solvent.

In this embodiment, in consideration of the temperature at which thea-Si is formed, i.e., at around 300° C., the baking temperature is setto 200° C. to be lower than 300° C. as in the first embodiment.According to the structure of the present embodiment, the conductorforming layer 123 to be formed into the conductor layer 122 is made ofMo. Therefore, Al which constitutes the source electrode 17 or the drainelectrode 18 can be prevented from being diffused into the semiconductorlayer. Therefore, even after having gone through the baking step,diffusion into the semiconductor layer made of Al can be suppressed tobe small, without hardly affecting the characteristics of the TFT inpractice.

[Channel Section Processing Step 143]

This step is carried out for processing the TFT channel section 72, asshown in FIGS. 43(a) through 43(c). FIGS. 43(a) through 43(c) arecross-sectional views corresponding to a portion taken along the lineO-O of FIG. 42(b).

As illustrated in FIG. 43(a), the wiring guide 71 of the channel section72 is removed by an organic solvent or by ashing.

Next, as shown in FIG. 43(b), a part of the conductor forming layer 123is selectively removed using the source electrode 17 and the drainelectrode 18 as a mask, thereby obtaining a conductor layer 122. In thisstep, a wet-etching method is adopted using nitric acid with weightpercent of 25%. Here, the portion from which the conductor forming layer123 is removed is formed in an opening section 122 a of the conductorlayer 122. With this opening section 122 a, the semiconductor layer 16is exposed from the channel section 72. Namely, the opening section 122a is formed in such a manner that the source electrode 17 and the drainelectrode 18 are electrically separated in the channel section 72 of theTFT section 22.

In the present embodiment, Al is adopted for the material of the sourceelectrode 17 and the drain electrode 18, and under the foregoing etchingconditions, no damage is observed. It is therefore possible toselectively remove only the part of the conductor forming layer 123. Itshould be noted here, however, that the etching method, and conditionsof the conductor forming layer 123 are not limited to the above. Theconductions which permit a selective etching of the conductor forminglayer 123 may be set in consideration of a material of the conductorforming layer 123, and materials of the source electrode 17, the drainelectrode 18, and the gate insulation layer 15. Similarly, although thewet etching method is adopted in the present embodiment, the dry etchingmethod may be adopted under appropriate conditions.

Next, as shown in FIG. 43(c), the n+ layer 69 around the opening section122 a is subjected to oxidation treatment by ashing or by using a laserso as to be a nonconductor.

In the present embodiment, Mo is adopted for the conductor layer 122 asfor the conductor forming layer 123. This conductor layer 122 is formedbetween the source electrode 17 or the drain electrode 18 and thesemiconductor layer 16. Therefore, the semiconductor layer 122 serves asan anti-diffusion layer for preventing Al of the materials whichconstitute the source electrode 17 or the drain electrode 18 from beingdiffused into the semiconductor layer 16.

Therefore, according to the present embodiment, after having gonethrough the substrate heating process to be carried out following thechannel section processing step 143, Al can be prevented from beingdiffused into the semiconductor layer 16 with almost no substantialeffects on the characteristics of the TFT. The substrate heating stepspecifically denotes, for example, the step of forming SiO₂ film,forming the photosensitive acrylic acid layer 20 in the protective filmforming step 48, the step of baking the ITO fine particle material inthe pixel electrode forming step 50.

As explained in the source/drain lines applying/forming step 142, byadopting, for example, Mo for the material of the conductor layer 122,which offers the effect of preventing Al from being diffused into thesemiconductor layer 16, the same effect can be appreciated for theconductor forming layer 123 to be formed into the conductor layer 122.Therefore, in the step of baking the substrate at 200° C. added to thesource/drain applying/forming step 142, Al can be prevented from beingdiffused into the semiconductor layer 16, without hardly affecting thecharacteristics of TFTs in practice.

The material for the source electrode 17 and the drain electrode 18 isnot limited to Al, and, for example, a metal material including Al as amain element, for example, an Al alloy may be adopted. In this case, thesemiconductor layer 122 made of Mo serves to prevent Al of the Al alloyand/or an element other than Al in the alloy from being diffused intothe semiconductor layer 16.

In the case of adopting a material like Al, which is liable to bediffused, for the source electrode 17 and the drain electrode, theproductivity would be significantly reduced by the conventional methodof separately forming the anti-diffusion layer after forming thesemiconductor layer 16, such as the method of forming the sourceelectrode 17 or the drain electrode 18 of a double layer structure of ananti-diffusion layer and a low electric resistance layer on the side ofthe glass substrate 12.

In contrast, according to the present embodiment, by making thesemiconductor layer 122 or the conductor forming layer function as ananti-diffusion layer, the process of separately forming theanti-diffusion layer can be omitted, thereby achieving a significantimprovement in productivity.

The effect as achieved from the structure of the present embodiment isappreciated particularly when adopting the inkjet method or otherapplication method for the source electrode 17 and the drain electrode18. When adopting the application method, the material applied for thefirst layer needs to be fixed completely before applying the materialfor the second layer. For this reason, the heating step needs to beperformed after applying the material for the first layer beforeapplying the material for the second layer. In this case, suchcomplicated process as transporting the substrate once processed withthe application device to the baking equipment, and then carrying thesubstrate again to the application device is needed, which significantlylowers the productivity. In contrast, according to the method of thepresent embodiment, the source electrode 17 and the drain electrode 18can be formed by a single application, and thus such problems associatedwith the conventional method that elements in the material or substancesof the source electrode 17 or the drain electrode 18 are diffused intothe semiconductor layer 16 which leads to lower productivity can beeliminated.

According to the structure of the present embodiment, it is possible tomake the conductor forming layer 123 to be formed into the conductorlayer 122 function as a pattern mask for use in forming thesemiconductor layer 16 and as an anti-diffusion layer for preventing thediffusion into the semiconductor layer 16. Further, it is possible tomake the conductor layer 122 itself function as an anti-diffusion layer.

Therefore, it is possible to adopt a metal material which is liable tobe diffused into the semiconductor layer 16 for the source electrode 17and the drain electrode 18 without a problem of a reduction inproductivity.

As described, according to the manufacturing method of the TFT arraysubstrate 121 of the present embodiment, the required number of maskscan be reduced as compared to the conventional manufacturing methodwhich does not adopt the pattern forming equipment by the inkjet method,from five to three, thus the manufacturing method of the presentembodiment significantly reduced the required number of photolithographyprocesses and the vacuum deposition devices. On this account, equipmentoutlay can also be greatly reduced. Furthermore, according to themanufacturing method of the present embodiment, a material, which isliable to be diffused into the semiconductor layer 16, can be adoptedfor the source electrode 17 and the drain electrode 18 without a problemof a reduction in productivity.

Here, the features explained in the fifth embodiment, such as the TFTarray substrate shown in FIG. 39 or the manufacturing method shown inFIG. 40 can be combined with the features explained in the first throughfourth embodiments provided that no contradiction arises.

For example, the TFT array substrate of the fifth embodiment may bearranged such that the TFT section gate electrode 66 of the thin filmtransistor section 22 is a branch electrode branched out from the mainline of the gate electrode 13, and the open end of this branch electrodeis protruded from the area of the semiconductor layer 16.

It may be arranged such that a part of the branch electrode protrudedfrom the area of the semiconductor layer has a smaller width than a partof the branch electrode within the area of the semiconductor layer.

It may be arranged such that the source electrode 17 and the drainelectrode 18 are formed on the semiconductor layer 16, and the channelsection 72 is formed between the source electrode 17 and the drainelectrode 18, and the part of the branch electrode protruded from thearea of the semiconductor layer 16 is formed in a vicinity of either thesource electrode 17 or the drain electrode 18.

It may be arranged such that on the semiconductor layer 16, the sourceelectrode 17 and the drain electrode 18 are formed, and the channelsection 72 is formed between the source electrode 17 and the drainelectrode 18, and the part of the branch electrode protruded from thesemiconductor layer 72 is formed with the condition given by thefollowing formula (1),L3>r+Δ1+2Δ2  (1)

where r denotes a distance from the center of the channel section 72 tothe outermost end of the channel section 72, Δ1 denotes the first errorin consideration of variations in amount of a droplet to be formed intothe semiconductor layer 16 and variations in spread of the droplet, Δ2denotes the second error in consideration of the displacement of adropped position of the droplet from the target position, and L3 denotesa distance from the center of the channel section to the open end of thebranch electrode.

It may be arranged such that on the semiconductor layer 16, the sourceelectrode 17 and the drain electrode 18 are formed, and the channelsection 72 is formed between the source electrode 17 and the drainelectrode 18, and the portion of the branch electrode protruded from thesemiconductor layer 16 is formed with the condition given by thefollowing formula (2),L2>Δ1+2Δ2  (2)

where Δ1 denotes the first error in consideration of variations inamount of a droplet to be formed into the semiconductor layer 16 andvariations in spread of the droplet, Δ2 denotes the second error inconsideration of the displacement of a dropped position of the dropletfrom the target position, and L2 denotes a distance from the endportions on the open end side of the branch electrode of the source anddrain electrodes to the open end of the branch electrode.

It may be arranged such that the source electrode 17 and the drainelectrode 18 are formed on the semiconductor layer 16, and the channelsection 72 is formed between these electrodes, further the end on thechannel section 72 in the source electrode 17 and the drain electrode 18are formed to the entire width in the region where the semiconductorlayer 16 is formed.

It may be further arranged such that a light blocking film in a dropletform is formed in a position corresponding to the position where thesemiconductor layer 16 is formed, either in the upper layer or the lowerlayer of the semiconductor layer 16.

It may be arranged such that on the semiconductor layer 16, the sourceelectrode 17 and the drain electrode 18 are formed, and the channelsection 72 is formed between the source electrode 17 and the drainelectrode 18, and the semiconductor layer 16 is formed with thecondition given by the following formula (3),R>r+Δ1+Δ2  (3)

where r denotes a distance from the center of the channel section to theoutermost end of the channel section, Δ1 denotes the first error inconsideration of variations in amount of a droplet to be formed into thesemiconductor layer 16 and variations in spread of the droplet, Δ2denotes the second error in consideration of the displacement of adropped position of the droplet from the target position, and R denotesa radius of the semiconductor layer, which is set according to thedistance from the center of the channel section 72.

The manufacturing method of the TFT array substrate of the fifthembodiment may be arranged such that the TFT section gate electrode 66of the thin film transistor section 22 is a branch electrode branchedout from the main line of the gate electrode 13, and the open end ofthis branch electrode is protruded from the area of the semiconductorlayer 16.

Further, it may be arranged such that the length of the branch electrodeis set so that the open end thereof can be protruded from thesemiconductor layer 16 in consideration of a dropping precision.

It may be arranged such that the part of the branch electrode protrudedfrom the area of the semiconductor layer has a smaller width than thepart of the branch electrode within the area of the semiconductor layer16.

It may be arranged such that the source electrode and the drainelectrode are formed on the semiconductor layer 16, and the channelsection 72 is formed between the source electrode 17 and the drainelectrode 18, and the portion of the branch electrode protruded from thearea of the semiconductor layer 16 is formed in a vicinity of either thesource electrode or the drain electrode.

In the manufacturing process of the gate electrode 13, the portion ofthe branch electrode protruded from area of the semiconductor layer 16may be formed with the condition given by the following formula (1),L3>r+Δ1+2Δ2  (1)

where r denotes a distance from the center of the channel section 72 tothe outermost end of the channel section 72, Δ1 denotes the first errorin consideration of variations in amount of a droplet to be formed intothe semiconductor layer 16 and variations in spread of the droplet, Δ2denotes the second error in consideration of the displacement of adropped position of the droplet from the target position, and L3 denotesa distance from the center of the channel section to the open end of thebranch electrode.

In the manufacturing process of the gate electrode 13, the portion ofthe branch electrode protruded from the semiconductor layer 72 may beformed with the condition given by the following formula (2),L2>Δ1+2Δ2  (2)

where Δ1 denotes the first error in consideration of variations inamount of a droplet to be formed into the semiconductor layer 16 andvariations in spread of the droplet, Δ2 denotes the second error inconsideration of the displacement of a dropped position of the dropletfrom the target position, and L2 denotes a distance from the endportions on the open end side of the branch electrode of the source anddrain electrodes to the open end of the branch electrode.

Further, the first and the second areas may be provided by forming aconvex guide which prevents flow of the droplet.

Further, the first and the second areas may be provided by forming alyophilic area and a lyophobic area respectively having a lyophiliccharacteristic and a lyophobic characteristic with respect to thedroplets.

The structure of the foregoing fifth embodiment may be combined with thestructure of each of the first through fourth embodiments, and suchcombination will offer the same function and effect as achieved thestructure of each of the first through fourth embodiments.

The TFT array substrate of the fifth embodiment is suitably applied to aliquid crystal display device; however, the TFT array substrate may beapplied to other display device such as a display device for an organicEL panel or an inorganic EL panel, etc., or a two-dimensional imageinput device represented by a fingerprint sensor, an x-ray imagingdevice, etc., or various electronic devices adopting the TFT arraysubstrate. The same can be said for the TFT array substrate adopted ineach of the first through fourth embodiments, and the TFT arraysubstrate is applicable to not only the liquid crystal display device,but also to other devices as listed above.

Similarly, the manufacturing method of the TFT array substrate of thefifth embodiment is suitably applied to the manufacturing method of theliquid crystal display device. However, the manufacturing method of thefifth embodiment is also applicable to the manufacturing method of otherdisplay device such as a display device for an organic EL panel or aninorganic EL panel, etc., or a two-dimensional image input devicerepresented by a fingerprint sensor, an x-ray imaging device, etc., orvarious electronic devices adopting the TFT array substrate. The samecan be said for the manufacturing method of the TFT array substrateadopted in each of the first through fourth embodiments, and themanufacturing method of the TFT array substrate is applicable to notonly the manufacturing method of liquid crystal display device, but alsoto the manufacturing method of other devices as listed above.

As described, the TFT array substrate according to the present inventionincludes a semiconductor layer having a shape formed by dropping adroplet.

On this account, the manufacturing of the TFT array substrate can beperformed without a mask for forming a semiconductor layer. As a result,the number of masks is reduced, thus reducing manufacturing processes.Further, the manufacturing requires less photolithography processesusing a mask, thus reducing equipment outlay for the photolithographyand amount of waste material. This allows reduction of time and costs ofmanufacturing.

The TFT array substrate may have such an arrangement that the gateelectrode in the thin film transistor section is a branch electrodewhich is branched out of a main line of the gate electrode, and thebranch electrode has an open end protruded from an area for thesemiconductor layer.

With the foregoing arrangement, since the open-end of the branchelectrode of the thin film transistor section is protruded from the areafor the semiconductor layer, a leak current between the source and drainelectrodes can be appropriately suppressed by the electrical field fromthe branch electrode.

The TFT array substrate according to the present invention may have suchan arrangement that the branch electrode is arranged so that a portionprotruded from the area for the semiconductor layer is smaller in widththan a portion confined within the area for the semiconductor layer.

With the foregoing arrangement, the open-end of the branch electrodeoccupies less area of the pixel section, thus suppressing decrease ofaperture ratio.

The TFT array substrate according to the present invention may have suchan arrangement that the thin film transistor section further includes asource electrode and a drain electrode on the semiconductor layer, and achannel section is formed between the source and drain electrodes, andthe portion of the branch electrode protruded from the area for thesemiconductor layer is formed in contact with one of the source anddrain electrodes.

With the foregoing arrangement, since the portion of the branchelectrode protruded from the area for the semiconductor layer is formedin contact with one of the source and drain electrodes, the open-end ofthe branch electrode may be extended to be out of the semiconductorlayer, without decreasing the aperture ratio of the pixel section of theTFT array substrate.

By adopting this arrangement, it is possible to securely provide thebranch electrode with an open-end protruded from the semiconductorlayer, thus securely suppressing the leak current between the source anddrain electrodes.

Further, the following formula may be referred to form the portionprotruded from the semiconductor layer.

Namely, the TFT array substrate according to the present invention mayhave such an arrangement that the thin film transistor section furtherincludes a source electrode and a drain electrode on the semiconductorlayer, and a channel section is formed between the source and drainelectrodes, and the portion of the branch electrode protruded from thearea for the semiconductor layer is formed according to the followingformula (1),L3>r+Δ1+2Δ2  (1)

where r denotes a distance from a center of the channel section to anoutermost end of the channel section, Δ1 denotes a first error takingaccount of variation of dropping amount of the droplet for forming thesemiconductor layer and variation of spread of the droplet afterdropping, Δ2 denotes a second error taking account of dropping off atarget position, and L3 denotes a distance from the center of thechannel section to the open end of the branch electrode.

Further, the TFT array substrate according to the present invention mayhave such an arrangement that the thin film transistor section furtherincludes a source electrode and a drain electrode on the semiconductorlayer, and a channel section is formed between the source and drainelectrodes, and the portion of the branch electrode protruded from thearea for the semiconductor layer is formed according to the followingformula (2),L2>Δ1+2Δ2  (2)

where Δ1 denotes a first error taking account of variation of droppingamount of the droplet for forming the semiconductor layer and variationof spread of the droplet after dropping, Δ2 denotes a second errortaking account of dropping off a target position, and L2 denotes adistance from (1) an end of each of the source and drain electrodes,closer to the open end of the branch electrode, to (2) the open end ofthe branch electrode.

The foregoing TFT array substrate may have such an arrangement that thethin film transistor section further includes a source electrode and adrain electrode on the semiconductor layer, and a channel section isformed between the source and drain electrodes, and the source and drainelectrodes each have an end that is positioned closer to the channelsection, and confined over an entire width within the area for thesemiconductor layer.

With the foregoing arrangement, the source electrode of each pixel canbe supplied with a sufficient ON current, thus preventing nonuniformityof charging condition of the pixel, which causes unevenness of theimage.

The TFT array substrate according to the present invention may have suchan arrangement that the thin film transistor section further includes alight-blocking film on either of an upper layer or an lower layer of thesemiconductor layer, the light-blocking film having a shape formed bydropping a droplet, and being formed on a portion corresponding to theposition of the semiconductor layer.

With the foregoing arrangement, when the light-blocking film isrequired, it can be created easily by dropping a droplet(s) of alight-blocking film material by using an inkjet method or the like.Accordingly, as with the forming of the semiconductor layer, thelight-blocking film can be formed without a mask. On this account, it isnot necessary to use extra number of masks or larger amount of materialin the manufacturing of the TFT array substrate, thus reducingmanufacturing steps and costs.

The TFT array substrate according to the present invention may have suchan arrangement that the thin film transistor section further includes asource electrode and a drain electrode on the semiconductor layer, and achannel section is formed between the source and drain electrodes, andthe semiconductor layer is formed according to the following formula(3),R>r+Δ1+Δ2  (3)

where r denotes a distance from a center of the channel section to anoutermost end of the channel section, Δ1 denotes a first error takingaccount of variation of dropping amount of the droplet for forming thesemiconductor layer and variation of spread of the droplet afterdropping, Δ2 denotes a second error taking account of dropping off atarget position, and R denotes a radius of the semiconductor layer,which extends from the center of the channel section.

With the foregoing arrangement, the semiconductor layer can be securelyprovided in the channel section of the thin film transistor section,thus ensuring desirable level of the characteristics of the thin filmtransistor section.

The liquid crystal display device of the present invention includes theforegoing TFT array substrate. Therefore, the manufacturing of theliquid crystal display requires less number of masks, thus reducing timeand costs of manufacturing.

A manufacturing method of the TFT array substrate according to thepresent invention includes the steps of: (a) forming a gate electrode ona substrate; (b) forming a gate insulation layer on the gate electrode;(c) depositing a semiconductor film on the gate insulation layer; (d)forming a resist layer having a shape of a droplet by dropping a dropletof a resist material on the semiconductor film; and (e) removing theresist layer, after processing the semiconductor film corresponding tothe shape of the resist layer so as to create a semiconductor layer of athin film transistor section.

In this manner, a resist layer is formed on a deposited semiconductorfilm by dropping a droplet of a resist material, and the semiconductorlayer is formed by using this resist layer having the shape of thedroplet (normally a circular shape) as a mask.

Accordingly, the forming of the semiconductor layer does not require amask, and therefore, the total required number of masks is reduced, thusreducing manufacturing processes.

Further, since the manufacturing requires less photolithographyprocesses using a mask, it is possible to reduce equipment outlay forthe photolithography and amount of waste material. This allows reductionof time and costs of manufacturing.

A manufacturing method of the TFT array substrate according to thepresent invention includes the steps of: (a) forming a gate electrode ona substrate; (b) forming a gate insulation layer on the gate electrode;and (c) forming a semiconductor layer having a shape of a droplet as asemiconductor layer of a thin film transistor section, by dropping adroplet of a semiconductor material on the gate insulation layer on thebranch electrode.

In this manner, the semiconductor layer is formed in a shape of adroplet (normally a circular shape) by only dropping a droplet of asemiconductor material on the gate insulation layer of the branchelectrode.

Accordingly, the forming of the semiconductor layer does not require amask, and therefore, the total required number of masks is reduced, thusreducing manufacturing processes.

Further, since the manufacturing requires less photolithographyprocesses using a mask, it is possible to reduce equipment outlay forthe photolithography and amount of waste material. This allows reductionof time and costs of manufacturing.

The foregoing manufacturing method of the TFT array substrate accordingto the present invention may be arranged so that: in the step (a), thegate electrode is formed so that the gate electrode includes a main lineand a branch electrode branched out of the main line, the branchelectrode having an open end protruded from an area for thesemiconductor layer.

With the foregoing arrangement, since the branch electrode of the gateelectrode of the thin film transistor section has an open-end protrudedfrom the area for the semiconductor layer, a leak current between thesource and drain electrodes can be appropriately suppressed by theelectrical field from the branch electrode.

The foregoing manufacturing method of the TFT array substrate may bearranged so that: the branch electrode is specified by length accordingto dropping accuracy of the droplet so that the open end is protrudedfrom the area for the semiconductor layer.

In this manner, the droplet of a resist material or a semiconductormaterial is dropped in a position for allowing the open-end of thebranch electrode to be protruded from the area for the completedsemiconductor. Thus, the leak current between the source and drainelectrodes can be appropriately suppressed.

The manufacturing method of the TFT array substrate according to thepresent invention may be arranged so that: the branch electrode isformed so that a portion protruded from the area for the semiconductorlayer is smaller in width than a portion confined within the area forthe semiconductor layer.

With the foregoing arrangement, the open-end of the branch electrodeoccupies less area of the pixel section, thus suppressing decrease ofaperture ratio.

The manufacturing method of the TFT array substrate according to thepresent invention may be arranged so that: the portion of the branchelectrode protruded from the area for the semiconductor layer is formedin contact with one of source and drain electrodes of the thin filmtransistor section.

With the foregoing arrangement, since the portion of the branchelectrode protruded from the area for the semiconductor layer is formedin contact with one of the source and drain electrodes, the open-end ofthe branch electrode may be extended to be out of the semiconductorlayer, without decreasing the aperture ratio of the pixel section of theTFT array substrate.

By adopting this arrangement, it is possible to securely provide thebranch electrode with an open-end protruded from the semiconductorlayer, thus securely suppressing the leak current between the source anddrain electrodes.

The manufacturing method of the TFT array substrate according to thepresent invention may be arranged so that: in the step (a), the branchelectrode is formed so that a portion protruded from the area for thesemiconductor layer is formed according to the following formula (1),L3>r+Δ1+2Δ2  (1)

where r denotes a distance from a center of the channel section to anoutermost end of the channel section, Δ1 denotes a first error takingaccount of variation of dropping amount of the droplet for forming thesemiconductor layer and variation of spread of the droplet afterdropping, Δ2 denotes a second error taking account of dropping off atarget position, and L3 denotes a distance from the center of thechannel section to the open end of the branch electrode.

Further, in the step (a), the branch electrode is formed so that aportion protruded from the area for the semiconductor layer is formedaccording to the following formula (2),L2>Δ1+2Δ2  (2)

where Δ1 denotes a first error taking account of variation of droppingamount of the droplet for forming the semiconductor layer and variationof spread of the droplet after dropping, Δ2 denotes a second errortaking account of dropping off a target position, and L2 denotes adistance from (1) an end of each of the source and drain electrodes,closer to the open end of the branch electrode, to (2) the open end ofthe branch electrode.

In both of the foregoing arrangements, it is possible to securelyprovide the branch electrode with an open-end protruded from thesemiconductor layer, thus securely suppressing the leak current betweenthe source and drain electrodes.

The manufacturing method of the TFT array substrate according to thepresent invention may be arranged so that: in the step (d), the resistlayer is formed according to the following formula (3),R>r+Δ1+Δ2  (3)

where r denotes a distance from a center of the channel section to anoutermost end of the channel section, Δ1 denotes a first error takingaccount of variation of dropping amount of the droplet for forming thesemiconductor layer and variation of spread of the droplet afterdropping, Δ2 denotes a second error taking account of dropping off atarget position, and R denotes a radius of the semiconductor layer,which extends from the center of the channel section.

With the foregoing arrangement, the semiconductor layer can be securelyprovided in the channel section of the thin film transistor section,thus ensuring desirable level of the characteristics of the thin filmtransistor section.

A manufacturing method of a TFT array substrate according to the presentinvention includes the steps of: (a) forming a gate electrode on asubstrate; (b) forming a gate insulation layer on the gate electrode;(c) forming a semiconductor layer of a thin film transistor section onthe gate insulation layer; (d) forming a first area to which a sourceelectrode is formed, and a second area to which at least a pixelelectrode is formed, by dropping a droplet of an electrode material onthe substrate after subjected to the step (c); and (e) forming a sourceelectrode, a drain electrode, and a pixel electrode in the first and thesecond areas by dropping droplets of an electrode material on thesubstrate after subjected to the step (d).

In this manner, the first area to which a source electrode is formed bydropping a droplet of an electrode material, and the second area towhich at least a pixel electrode is formed by dropping a droplet of anelectrode material are formed in one process for pre-processing of theelectrode forming step. Therefore, the manufacturing processes and costscan be reduced compared to the case of separately forming the first andthe second areas in different steps.

A manufacturing method of a liquid crystal display device according tothe present invention includes one of the foregoing manufacturingmethods of a TFT array substrate. Therefore, it is possible to reduce atleast manufacturing processes for producing a liquid crystal displaydevice, thus reducing costs.

A TFT array substrate according to the present invention includes: athin film transistor section in which a gate electrode is formed on asubstrate, and a semiconductor layer and a conductor layer are formed onthe gate electrode via a gate insulation layer, wherein: the conductorlayer is formed in contact with the semiconductor layer and one ofsource and drain electrodes of the thin film transistor section, and hasa portion formed by dropping a droplet, the conductor layer and thesemiconductor layer having substantially the same shape in the portionformed by dropping a droplet.

In this arrangement, a conductor forming layer is formed on a depositedsemiconductor film by dropping a droplet of a conductive material, andthe semiconductor layer is formed by using this conductor forming layerhaving the shape of the droplet (normally a circular shape) as a mask.This conductor forming layer is not required to be removed unlike theresist layer, and therefore, the removal process can be omitted. In thisarrangement, the dropping of the droplet of a conductive material ontothe semiconductor layer can be carried out by an inkjet method, forexample, or by any methods enabling formation of a droplet having anappropriate size for a semiconductor layer of the thin film transistorsection.

With this arrangement of a TFT array substrate, the semiconductor layercan be formed without a mask; and therefore the required number of masksis reduced. Further, the conductor forming layer is not required to beremoved unlike the resist layer, and therefore the removal process canbe omitted, thus greatly reducing manufacturing processes and equipmentoutlay. Moreover, the required amount of chemicals, such as a developeror removing agent can also be reduced, as well as amount of waste of theresist material etc. On this account, it is possible to reduce the timeand costs of manufacturing.

Further, the conductor layer may be constituted of Mo, W, Ag, Cr, Ta,Ti, a metal material mainly containing one of Mo, W Ag, Cr, Ta, Ti, oran indium tin oxide.

More specifically, with the foregoing arrangement, the conductor layer,provided between the semiconductor layer and the source or drainelectrode, operates as a diffusion preventing layer for practicallypreventing diffusion of a component element(s) constituting the sourceelectrode or the drain electrode. Further, the conductor forming layer,which is a previous state of the conductor layer, also operates as thediffusion preventing layer. By thus practically preventing diffusion,the diffusion amount of the materials to the semiconductor layer issmall even after heat treatment, so that there is few practicalinfluence of the diffusion to the characteristic of the TFT.

The foregoing configuration of the present invention can deal with sucha circumstance of recent years that a source or drain electrode is oftenmade of Al, Cu or the like, which is likely to diffuse into thesemiconductor layer. Therefore, the configuration of the presentinvention has a wider selection range of materials for constituting asource or drain electrode, while hardly increasing the number ofmanufacturing processes.

With this arrangement, manufacturing processes can be greatly reducedcompared to the conventional method for forming a diffusion preventinglayer after the semiconductor layer, for example, a method in which thesource and drain electrodes are respectively constituted of a diffusionpreventing layer and a low electric resistance layer, in this order fromthe glass substrate. On this account, productivity of the TFT arraysubstrate can be improved.

Particularly, it is effective in terms of manufacturing that the sourceand drain electrodes are made of an Al or a metal material mainlycontaining Al.

As one of their characteristics, an Al or the metal material mainlycontaining Al are not easily damaged by an oxidative acid, such as anitric acid. Thus, the conductor forming layer is preferably made of anAg, Mo, W, or an alloy mainly containing an Ag, Mo, W, which are solubleby an oxidative acid such as a nitric acid. This arrangement isadvantageous in manufacturing, since the wet-etching can be carried outonly for the conductive forming layer with desirable selectivity byusing an oxidative acid, such as a nitric acid.

Further, since the source and drain electrodes made of an Al or themetal material mainly containing Al have a low electric resistance.Therefore the TFT array substrate can be compatible with a recentlarge-sized TFT array substrate.

Further, the liquid crystal display device according to the presentinvention includes the foregoing TFT array substrate. Therefore, it ispossible to reduce manufacturing processes of a TFT array substrate,thus reducing the time and costs of manufacturing.

A manufacturing method of a TFT array substrate according to the presentinvention includes the steps of: (a) forming a gate electrode on asubstrate; (b) forming a gate insulation layer on the gate electrode;(c) depositing a semiconductor film on the gate insulation layer; (d)forming a conductor forming layer having a shape of a droplet bydropping a droplet of a conductive material on the semiconductor film;and (e) forming a semiconductor layer of a thin film transistor sectionby processing the semiconductor film corresponding to the shape of theconductor forming layer.

In this arrangement, a conductor forming layer is formed on a depositedsemiconductor film by dropping a droplet of a conductive material, andthe semiconductor layer is formed by using this conductor forming layerhaving the shape of the droplet (normally a circular shape) as a mask.This conductor forming layer is not required to be removed unlike theresist layer, and therefore, the removal process can be omitted.

With this arrangement of a TFT array substrate, the semiconductor layercan be formed without a mask; and therefore the required number of masksis reduced, thus reducing manufacturing processes. Further, themanufacturing requires less photolithography processes using a mask,thus reducing equipment outlay for the photolithography, thus greatlyreducing manufacturing processes and equipment outlay. Moreover, therequired amount of chemicals, such as a developer or removing agent canalso be reduced, as well as amount of waste of the resist material etc.On this account, it is possible to reduce the time and costs ofmanufacturing.

Further, the foregoing manufacturing method of a TFT array substrate mayfurther includes the step of: processing the conductor forming layer soas to form a conductor layer, wherein: the conductor layer isconstituted of Mo, W, Ag, Cr, Ta, Ti, a metal material mainly containingone of Mo, W, Ag, Cr, Ta, Ti, or an indium tin oxide.

With this method, the configuration of the present invention has a widerselection range of materials for constituting a source or drainelectrode, while hardly increasing the number of manufacturingprocesses. More specifically, the conductor forming layer as a previousstate of the conductor layer operates as a pattern mask for forming thesemiconductor layer and also as a diffusion preventing layer forpreventing the diffusion into the semiconductor layer.

Furthermore, the conductor layer created from the conductor forminglayer also has the diffusion preventing function. Accordingly, selectionrange of material becomes wider since the source and drain electrodesmay be made of an Al or an Cu, which have a low electrical resistance.

The source and drain electrodes are preferably made of an Al or a metalmaterial mainly containing Al.

Here, the conductor forming layer is preferably made of an Ag, Mo, W, oran alloy mainly containing an Ag, Mo, W, which are soluble by anoxidative acid such as a nitric acid.

This arrangement is advantageous in manufacturing, since the wet-etchingcan be carried out only for the conductive forming layer with desirableselectivity by using an oxidative acid, such as a nitric acid.

On this account, it is possible to, for example, reduce manufacturingprocesses of a TFT array substrate, thus improving productivity of a TFTarray substrate.

The manufacturing method of a liquid crystal display device according tothe present invention includes one of the foregoing manufacturingmethods of a TFT array substrate. Therefore, it is possible to reduce atleast manufacturing processes for producing a liquid crystal displaydevice.

For a fuller understanding of the nature and advantages of theinvention, reference should be made to the ensuing detailed descriptiontaken in conjunction with the accompanying drawings.

The invention being thus described, it will be obvious that the same waymay be varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

INDUSTRIAL APPLICABILITY

The TFT array substrate according to the present invention ismanufactured through an inkjet method. The TFT array substrate may beadopted for a field requiring reduction in costs and numbers ofmanufacturing processes. The TFT array substrate is particularlysuitable for a liquid crystal display device; however, it is alsocompatible with other display devices (such as an organic EL panel) or aimaging device.

1. A TFT array substrate, comprising: a thin film transistor section inwhich a gate electrode is formed on a substrate, and a semiconductorlayer is formed on the gate electrode via a gate insulation layer, theprocessed semiconductor layer having a shape formed by dropping adroplet.
 2. The TFT array substrate as set forth in claim 1, wherein:the gate electrode in the thin film transistor section is a branchelectrode which is branched out of a main line of the gate electrode,and the branch electrode has an open end protruded from an area for thesemiconductor layer.
 3. The TFT array substrate as set forth in claim 2,wherein: the branch electrode is arranged so that a portion protrudedfrom the area for the semiconductor layer is smaller in width than aportion confined within the area for the semiconductor layer.
 4. The TFTarray substrate as set forth in claim 2, wherein: the thin filmtransistor section further includes a source electrode and a drainelectrode on the semiconductor layer, and a channel section is formedbetween the source and drain electrodes, and the portion of the branchelectrode protruded from the area for the semiconductor layer is formedin contact with one of the source and drain electrodes.
 5. The TFT arraysubstrate as set forth in claim 2, wherein: the thin film transistorsection further includes a source electrode and a drain electrode on thesemiconductor layer, and a channel section is formed between the sourceand drain electrodes, and the portion of the branch electrode protrudedfrom the area for the semiconductor layer is formed according to thefollowing formula (1),L3>r+Δ1+2Δ2  (1) where r denotes a distance from a center of the channelsection to an outermost end of the channel section, Δ1 denotes a firsterror taking account of variation of dropping amount of the droplet forforming the semiconductor layer and variation of spread of the dropletafter dropping, Δ2 denotes a second error taking account of dropping offa target position, and L3 denotes a distance from the center of thechannel section to the open end of the branch electrode.
 6. The TFTarray substrate as set forth in claim 2, wherein: the thin filmtransistor section further includes a source electrode and a drainelectrode on the semiconductor layer, and a channel section is formedbetween the source and drain electrodes, and the portion of the branchelectrode protruded from the area for the semiconductor layer is formedaccording to the following formula (2),L2>Δ1+2Δ2  (2) where Δ1 denotes a first error taking account ofvariation of dropping amount of the droplet for forming thesemiconductor layer and variation of spread of the droplet afterdropping, Δ2 denotes a second error taking account of dropping off atarget position, and L2 denotes a distance from (1) an end of each ofthe source and drain electrodes, closer to the open end of the branchelectrode, to (2) the open end of the branch electrode.
 7. The TFT arraysubstrate as set forth in claim 1, wherein: the thin film transistorsection further includes a source electrode and a drain electrode on thesemiconductor layer, and a channel section is formed between the sourceand drain electrodes, and the source and drain electrodes each have anend that is positioned closer to the channel section, and confined overan entire width within the area for the semiconductor layer.
 8. The TFTarray substrate as set forth in claim 1, wherein: the thin filmtransistor section further includes a light-blocking film on either ofan upper layer or an lower layer of the semiconductor layer, thelight-blocking film having a shape formed by dropping a droplet, andbeing formed on a portion corresponding to the position of thesemiconductor layer.
 9. The TFT array substrate as set forth in claim 1,wherein: the thin film transistor section further includes a sourceelectrode and a drain electrode on the semiconductor layer, and achannel section is formed between the source and drain electrodes, andthe semiconductor layer is formed according to the following formula(3),R>r+Δ1+Δ2  (3) where r denotes a distance from a center of the channelsection to an outermost end of the channel section, Δ1 denotes a firsterror taking account of variation of dropping amount of the droplet forforming the semiconductor layer and variation of spread of the dropletafter dropping, Δ2 denotes a second error taking account of dropping offa target position, and R denotes a radius of the semiconductor layer,which extends from the center of the channel section.
 10. A liquidcrystal display device including the TFT array substrate as set forth inclaim
 1. 11. A manufacturing method of a TFT array substrate, comprisingthe steps of: (a) forming a gate electrode on a substrate; (b) forming agate insulation layer on the gate electrode; (c) depositing asemiconductor film on the gate insulation layer; (d) forming a resistlayer having a shape of a droplet by dropping a droplet of a resistmaterial on the semiconductor film; and (e) removing the resist layer,after processing the semiconductor film corresponding to the shape ofthe resist layer so as to create a semiconductor layer of a thin filmtransistor section.
 12. The manufacturing method of a TFT arraysubstrate as set forth in claim 11, wherein: in the step (a), the gateelectrode is formed so that the gate electrode includes a main line anda branch electrode branched out of the main line, the branch electrodehaving an open end protruded from an area for the semiconductor layer.13. The manufacturing method of a TFT array substrate as set forth inclaim 12, wherein: the branch electrode is specified by length accordingto dropping accuracy of the droplet so that the open end is protrudedfrom the area for the semiconductor layer.
 14. The manufacturing methodof a TFT array substrate as set forth in claim 12, wherein: the branchelectrode is formed so that a portion protruded from the area for thesemiconductor layer is smaller in width than a portion confined withinthe area for the semiconductor layer.
 15. The manufacturing method of aTFT array substrate as set forth in claim 12, wherein: the portion ofthe branch electrode protruded from the area for the semiconductor layeris formed in contact with one of source and drain electrodes of the thinfilm transistor section.
 16. The manufacturing method of a TFT arraysubstrate as set forth in claim 12, wherein: in the step (a), the branchelectrode is formed so that a portion protruded from the area for thesemiconductor layer is formed according to the following formula (1),L3>r+Δ1+2Δ2  (1) where r denotes a distance from a center of the channelsection to an outermost end of the channel section, Δ1 denotes a firsterror taking account of variation of dropping amount of the droplet forforming the semiconductor layer and variation of spread of the dropletafter dropping, Δ2 denotes a second error taking account of dropping offa target position, and L3 denotes a distance from the center of thechannel section to the open end of the branch electrode.
 17. Themanufacturing method of a TFT array substrate as set forth in claim 13,wherein: in the step (a), the branch electrode is formed so that aportion protruded from the area for the semiconductor layer is formedaccording to the following formula (2),L2>Δ1+2Δ2  (2) where Δ1 denotes a first error taking account ofvariation of dropping amount of the droplet for forming thesemiconductor layer and variation of spread of the droplet afterdropping, Δ2 denotes a second error taking account of dropping off atarget position, and L2 denotes a distance from (1) an end of each ofthe source and drain electrodes, closer to the open end of the branchelectrode, to (2) the open end of the branch electrode.
 18. Themanufacturing method of a TFT array substrate as set forth in claim 11,wherein: in the step (d), the resist layer is formed according to thefollowing formula (3),R>r+Δ1+Δ2  (3) where r denotes a distance from a center of the channelsection to an outermost end of the channel section, Δ1 denotes a firsterror taking account of variation of dropping amount of the droplet forforming the semiconductor layer and variation of spread of the dropletafter dropping, Δ2 denotes a second error taking account of dropping offa target position, and R denotes a radius of the semiconductor layer,which extends from the center of the channel section.
 19. Amanufacturing method of a TFT array substrate, comprising the steps of:(a) forming a gate electrode with a branch electrode on a substrate; (b)forming a gate insulation layer on the gate electrode; and (c) forming asemiconductor layer having a shape of a droplet as a semiconductor layerof a thin film transistor section, by dropping a droplet of asemiconductor material on the gate insulation layer on the branchelectrode.
 20. The manufacturing method of a TFT array substrate as setforth in claim 19, wherein: in the step (a), the gate electrode isformed so that the gate electrode includes a main line and a branchelectrode branched out of the main line, the branch electrode having anopen end protruded from an area for the semiconductor layer.
 21. Themanufacturing method of a TFT array substrate as set forth in claim 19,wherein: the step (c) includes the sub-steps of: (i) depositing asemiconductor film on the gate insulation layer; (ii) forming a resistlayer having a shape of a droplet by dropping a droplet of a resistmaterial on the semiconductor film; and (iii) removing the resist layer,after processing the semiconductor film corresponding to the shape ofthe resist layer so as to create a semiconductor layer of a thin filmtransistor section, and in the step (ii), the resist layer is formedaccording to the following formula (3),R>r+Δ1+Δ2  (3) where r denotes a distance from a center of the channelsection to an outermost end of the channel section, Δ1 denotes a firsterror taking account of variation of dropping amount of the droplet forforming the semiconductor layer and variation of spread of the dropletafter dropping, Δ2 denotes a second error taking account of dropping offa target position, and R denotes a radius of the semiconductor layer,which extends from the center of the channel section.
 22. Amanufacturing method of a TFT array substrate, comprising the steps of:(a) forming a gate electrode on a substrate; (b) forming a gateinsulation layer on the gate electrode; (c) forming a semiconductorlayer of a thin film transistor section on the gate insulation layer;(d) forming a first area to which a source electrode is formed, and asecond area to which at least a pixel electrode is formed, by dropping adroplet of an electrode material on the substrate after subjected to thestep (c); and (e) forming a source electrode, a drain electrode, and apixel electrode in the first and the second areas by dropping dropletsof an electrode material on the substrate after subjected to the step(d).
 23. The manufacturing method of a TFT array substrate as set forthin claim 22, wherein: the first and the second areas are provided byforming a convex guide which prevents flow of the droplet.
 24. Themanufacturing method of a TFT array substrate as set forth in claim 22,wherein: the first and the second areas are provided by forming alyophilic area and a lyophobic area respectively having a lyophiliccharacteristic and a lyophobic characteristic with respect to thedroplets.
 25. A manufacturing method of a liquid crystal display deviceincluding the manufacturing method of a TFT substrate as set forth inclaim
 11. 26. A TFT array substrate, comprising: a thin film transistorsection in which a gate electrode is formed on a substrate, and asemiconductor layer and a conductor layer are formed on the gateelectrode via a gate insulation layer, wherein: the conductor layer isformed in contact with the semiconductor layer and one of source anddrain electrodes of the thin film transistor section, and has a portionformed by dropping a droplet, the conductor layer and the semiconductorlayer having substantially the same shape in the portion formed bydropping a droplet.
 27. The manufacturing method of a TFT arraysubstrate as set forth in claim 26, wherein: the conductor layer isconstituted of Mo, W, Ag, Cr, Ta, Ti, a metal material mainly containingone of Mo, W, Ag, Cr, Ta, Ti, or an indium tin oxide.
 28. Themanufacturing method of a TFT array substrate as set forth in claim 27,wherein: the source and drain electrodes are made of an Al or a metalmaterial mainly containing Al.
 29. A liquid crystal display deviceincluding the TFT array substrate as set forth in claim
 26. 30. Amanufacturing method of a TFT array substrate, comprising the steps of:(a) forming a gate electrode on a substrate; (b) forming a gateinsulation layer on the gate electrode; (c) depositing a semiconductorfilm on the gate insulation layer; (d) forming a conductor forming layerhaving a shape of a droplet by dropping a droplet of a conductivematerial on the semiconductor film; and (e) forming a semiconductorlayer of a thin film transistor section by processing the semiconductorfilm corresponding to the shape of the conductor forming layer.
 31. Themanufacturing method of a TFT array substrate as set forth in claim 30,further comprising the step of: processing the conductor forming layerso as to form a conductor layer, wherein: the conductor layer isconstituted of Mo, W, Ag, Cr, Ta, Ti, a metal material mainly containingone of Mo, W, Ag, Cr, Ta, Ti, or an indium tin oxide.
 32. Themanufacturing method of a TFT array substrate as set forth in claim 31,wherein: the source and drain electrodes are made of an Al or a metalmaterial mainly containing Al.
 33. A manufacturing method of a liquidcrystal display device including the manufacturing method of a TFTsubstrate as set forth in claim
 30. 34. An electronic device includingthe TFT array substrate as set forth in claim
 1. 35. An electronicdevice including the TFT array substrate as set forth in claim 26.